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I/O Subsystem
Figure 88. Voltage Translation Circuit for 3.3-V Receivers
10.7.2.
In Circuit FWH Programming
All cycles destined for the FWH will appear on PCI. The ICH4-M hub interface to PCI Bridge will put
all CPU boot cycles out on PCI (before sending them out on the FWH interface). If the ICH4-M is set
for subtractive decode, these boot cycles can be accepted by a positive decode agent on the PCI bus.
This enables the ability to boot from a PCI card that positively decodes these memory cycles. In order to
boot from a PCI card, it is necessary to keep the ICH4-M in subtractive decode mode. If a PCI boot card
is inserted and the ICH4-M is programmed for positive decode, there will be two devices positively
decoding the same cycle.
10.7.3.
FWH INIT# Voltage Compatibility
The FWH INIT# signal trip points need to be considered because they are NOT consistent among
different FWH manufacturers. The INIT# signal is active low. Therefore, the inactive state of the Intel
ICH4-M INIT# signal needs to be at a value slightly higher than the V
specification. The inactive state of this signal is typically governed by the formula V_CPU_IO(min) –
noise margin. Therefore if the V_CPU_IO(min) of the processor is 1.60 V, the noise margin is 200 mV
and the V
IH
because 1.6 V - 0.2 V = 1.40 V which is greater than the 1.35 V minimum of the FWH. If the V
of the FWH was 1.45 V, then there would be an incompatibility and logic translation would need to be
used. The examples above do not take into account any noise that may be encountered on the INIT#
signal. Care must be taken to ensure that the V
applications where it is necessary to use translation logic, refer to Section 4.3.4.7.
The solution assumes that level translation is necessary. The Figure 16 implements a UP topology
solution for the Intel Pentium 4 processor-M / Mobile Intel Celeron processor and Intel ICH4-M FWH
signal INIT#. Trace lengths and resistor values can be found in
Table 11. The Voltage Translator circuitry is shown in Figure 17. Figure 29 implements a UP topology
solution for the Intel Celeron M processor and Intel ICH4-M FWH signal INIT#. Trace lengths and
resistor values can be found in Table 27. The Voltage Translator circuitry is shown in Figure 30.
174
1.3K ohm
330 ohm
+/- 5%
From Driver
Rs
min spec of the FWH INIT# input signal is 1.35 V, there would be no compatibility issue
3.3V
330 ohm
+/- 5%
R1
+/- 5%
Q2
Q1
3904
min specification is met with ample noise margin. In
IH
®
Intel
852GM Chipset Platform Design Guide
3.3V
R2
To Receiver
3904
min FWH INIT# pin
IH
R
min
IH
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