Intel 852GM Design Manual page 308

Chipset platform
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A
15,17,23,27,44
+V3.3_LPCSLOT
19,33
SUS_CLK
4
5,15,19..23,27..29,32,36,38,39,44,48
+V3.3ALWAYS
18,32
H_RCIN#
32,36
KBC_A20GATE
19,32,34,36
SMC_EXTSMI#
+V5_LPCSLOT
19
LPC_DRQ#1
19,31..34
LPC_FRAME#
3
19,31..34
LPC_AD2
19,31..34
LPC_AD0
6
CLK_LPC14
R9G3
22,23,32
PCI_GATED_RST#
NO_STUFF_0
2
5,19,21,32
PM_THRM#
19,32
PM_PWRBTN#
32,44
SMC_ONOFF#
32,39,42
VR_ON
19,21,25,32,39
PM_PWROK
19,21,32
PM_RSMRST #
32,44
AC_PRESENT#
19,25,32,38,43,44
PM_SLP_S3#
44,48
GATED_SMC_SHUTDOWN
32
BAT_SUSPEND
32
SMC_RSTGATE#
24,32,36
DOCK_INTR#
1
20..23,27,36,42..44
+V5
R9G1
0.01_1%
A
B
LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD
+V12S
LPC Debug Slot
+V3.3_LPCSLOT
15,17,23,27,44
+V12S
J8F1
B1
A1
12V1
12V2
B2
A2
SUSCLK
NEG_12V
B3
A3
GND1
GND2
B4
A4
LREQ
BP_CLK
B5
A5
VCC3_1
VCC3_2
B6
A6
LCNTL0
LCNTL1
B7
A7
GND3
GND5
B8
A8
LDC
LD6
B9
A9
LD5
LD4
B10
A10
GND4
GND7
B11
A11
LD3
LD2
B12
A12
LD1
LD0
B13
A13
GND6
VCC5_2
B14
A14
3V_STBY
SCLK
B15
A15
LPS
GND10
B16
A16
KBRESTE#
SERIRQ
B17
A17
A20GATE#
CLKRUN#
B18
A18
GND8
GND12
5,15,19..23,27..29,32,36,38,39,44,48
B19
A19
LSMI#
LINK_ON
KEY
B20
A20
VCC5_1
VCC5_3
B21
A21
LDRQ1#
LDRQ0#
B22
A22
LFRAME1#
GND14
B23
A23
GND9
LAD3
B24
A24
LAD2
LAD1
B25
A25
LAD0
GND15
B26
A26
GND11
PCICLK
B27
A27
PCIRST#
LPCPD#
B28
A28
GND13
GND16
B29
A29
OSC
PME#
B30
A30
VCC3_3
VCC3_4
60Pin_CardCon
Layout Note:
Line up LPC slot
with PCI Slot 3
R9G4
BUF_PCI_RST# 18,22..24,26,31,32,34
0
J9D2
1
2
SMC_RUNTIME_SCI#
3
4
SMC_WAKE_SCI# 19,32,36
5
6
FAN_ON
7
8
SMB_THRM_CLK 5,32
9
10
SMB_THRM_DATA 5,32
11
12
13
14
SMB_SB_CLK 32,36,44
15
16
SMB_SB_DATA 32,36,44
17
18
SMB_SB_ALRT# 32,36,44
19
20
PM_BATLOW# 19,32,36
21
22
23
24
25
26
27
28
SMB_SC_INT# 32
29
30
15x2_HDR
SMC Sidebands for LPC Power Management
+V5_LPCSLOT
+V3.3
R9G5
C9G2
C9G1
22UF
0.1UF
B
C
18,21
19,21,35
3,7,18
18,21
+V5_LPCSLOT
INT_SERIRQ 18,22..24,32,34
PM_CLKRUN# 19,21..24,32,34
+V3.3ALWAYS
R8G9
10K
LPC_DRQ#0 19
LPC_AD3 19,31..34
LPC_AD1 19,31..34
CLK_LPCPCI 6
PM_SUS_STAT# 19,32,34,48
PCI_PME# 15,18,22,23
19,32,36
32,38
15,18..20,23,27,30,32,35,38,39,43,44
+V3.3_LPCSLOT
0.01_1%
C9G4
C8F1
C8F3
C9G3
22UF
0.1UF
0.1UF
0.1UF
C
D
J3H1
1
2
3
4
4,18
H_PWRGD
5
6
SM_INTRUDER#
7
8
PM_RI#
9
10
H_DPSLP#
11
12
SMB_ALERT#
13
14
3,18
H_NMI
15
16
3,18
H_SMI#
2X8_HDR
20,21
+V3.3ALWAYS_ICH
19..22,24
+V3.3S_ICH
R7J3
R7J4 10K
4.7K
J7J1
1
2
19
ICH_GPIO7
3
4
5
6
18,21..23
INT_PIRQH#
7
8
19
ICH_MFG_MODE
9
10
15,18,22,23
PCI_PME#
2X5-Header
ICH4-M Testpoint Header
J9J1
1
2
6,19,39,40
PM_STPCPU#
3
4
6,19,38,44
PM_SLP_S1#
5
6
19,48
PM_C3_STAT#
7
8
3,19
PM_CPUPERF#
9
10
39
VR_PWRGD
11
12
13
14
15
16
2X8_HDR
J2J2
1
2
27,34
IDE_SPWR_EN#
3
4
5
6
7
8
8Pin HDR
SIO Sidebands
TEST HEADER
J2J1
1
2
19,32,34,36
SMC_EXTSMI#
3
4
19,38
PM_SLP_S5#
5
6
19,39,40
PM_DPRSLPVR
7
8
8Pin HDR
NO STUFF
GROUND
HEADERS
J9J4
J7E1
1
2
1
2
J9J3
1
2
Title
LPC Slot & Debug Headers
Size
Project:
A
Intel 852GM CRB
D
E
H_INIT#
3,18
+V5
H_INTR
3,18
BUF_PCI_RST# 18,22..24,26,31,32,34
R4169_D
R3H3
1K
H_STPCLK# 3,18
H_CPUSLP# 3,18
IDE_PATADET 19,26
IDE_SATADET 19,26
PM_STPPCI# 6,19
INT_IRQ14 18,21,26
INT_IRQ15 18,21,26
AGP_SUSPEND# 19
PM_CLKRUN# 19,21..24,32,34
PM_SLP_S4# 19,20,32,38,43,44
FWH_WP# 19,31
FWH_TBL# 19,31
DELAYED_VR_PWRGD
19,40
PM_SUS_CLK 15,19
PM_GMUXSEL 19
J7F2
J1H6
J2A2
1
2
1
2
1
2
J7A1
J9E1
J1E2
1
2
1
2
1
2
Document Number
Rev
A#
37
of
59
E
20..23,2
4
3
2
1

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