Clock Routing Updates For "Ddp Stacked" Memory Device Support; Data Signals - Sdq[64:0], Sdm[7:0], Sdqs[7:0]; Figure 45. Clock Signal Routing Example - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)

Figure 45. Clock Signal Routing Example

7.3.3.4.1.

Clock Routing Updates for "DDP Stacked" Memory Device Support

Simulation results show that the current DDR layout and routing guidelines for Intel 852GM chipset-
based platforms can support "DDP stacked" SO-DIMM memory modules.
7.3.4. Data Signals – SDQ[64:0], SDM[7:0], SDQS[7:0]
The GMCH data signals are source synchronous signals that include a 64-bit wide data bus, a set of 8
data mask bits, and a set of 8 data strobe signals. There is an associated data strobe and data mask bit for
each of the 8-bit data byte groups, making for a total of nine – 10-bit byte lanes. This section
summarizes the SDQ/SDM to SDQS routing guidelines and length matching recommendations.
90
Clock
SO-DIMM0
S0-DIMM1
GMCH
®
Intel 852GM Chipset Platform Design Guide
R