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Intel 852GM Platform Power Delivery Guidelines
12.5.3.4.
DDR VTT Termination
The recommended topology for DDR-SDRAM Data, Control, and Command signal groups requires that
all these signals to be terminated to a 1.25-V source, VTT, at then end of the memory channel opposite
the GMCH. Intel recommends that this VTT be generated from the same source as used for VCCSM,
and not be used for GMCH and DDR SMVREF. This is because SMVREF has a much tighter tolerance
and VTT can vary more easily depending on signal states. A solid 1.25-V termination island should be
used to for this purpose and be placed on the surface signal layer, just beyond the last SO-DIMM
connector and must be at least 50 mils wide.
The Data and Command signals should be terminated using one resistor per signal. Resistor packs and ±
5% tolerant resistors are acceptable for this application. Only signals from the same DDR signal group
can share a resistor pack. See Chapter 6 for system memory guidelines.
12.5.3.5.
DDR SMRCOMP, SMVREF, and VTT 1.25-V Supply Disable in S3/Suspend
Regardless of how these 1.25-V supplies for GMCH are generated, they can be disabled during the S3
suspend state to further save power on the platform. This is possible because the GMCH does not
require a valid reference voltage nor does it require the enabling of resistive compensation during
suspend. However, some DDR memory devices may require a valid reference voltage during
suspend. It is the responsibility of the system designer to ensure that requirements of the DDR memory
devices are met. Note that the 2.5-V VCCSM power pins of the MCH-M and the VDD power pins of the
DDR memory devices do need to be on in S3 state.
12.5.4.
Other GMCH Reference Voltage and Analog Power Delivery
12.5.4.1.
GMCH GTLVREF
For GMCH, the GTLREF generation circuit has been broken down into three separate voltage
references; host data reference voltage (HDVREF[2:0]), host address reference voltage (HAVREF) and
host common clock reference voltage (HCCVREF). Maximum length from pin to voltage divider for
each reference voltage should be less than 0.5 inches. 10-mil wide traces are recommended. GMCH
VREF can be maintained as individual voltage dividers as shown in Figure 126, Figure 127, and Figure
128.
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Intel
852GM Chipset Platform Design Guide
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