Topology 2A: Open Drain (Od) Signals Driven By Ich4-M - Pwrgood; Figure 25. Routing Illustration For Topology 1C; Figure 26. Routing Illustration For Topology 2A; Table 23. Layout Recommendations For Topology 1C - Intel 852GM Design Manual

R

Figure 25. Routing Illustration for Topology 1C

Table 23. Layout Recommendations for Topology 1C

L1
0.5" – 12.0" 0" – 3.0" 0" – 3.0" 0.5" – 12.0" 330 Ω ± 5% 1.3 k Ω ± 5% 330 Ω ± 5% 56 Ω ± 5%
0.5" – 12.0" 0" – 3.0" 0" – 3.0" 0.5" – 12.0" 330 Ω ± 5% 1.3 k Ω ± 5% 330 Ω ± 5% 56 Ω ± 5%
5.5.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M –
PWRGOOD
The Topology 2A OD signal PWRGOOD, which is driven by the ICH4-M (CMOS signal input to
processor) should adhere to the following routing and layout recommendations. Table 24 lists the
recommended routing requirements for the PWRGOOD signal of the processor. The routing guidelines
allow the signal to be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace
impedance. The pull-up voltage for termination resistor Rtt is VCCP (1.05 V).
Note: The ICH4-M's CPUPWRGD signal should be routed point-to-point to the processor's PWRGOOD
signal. The routing from the processor's PWRGOOD pin should fork out to both to the termination
resistor, Rtt, and the ICH4-M. Segments L1 and L2 from Table 24 should not T-split from a trace from
the pin.

Figure 26. Routing Illustration for Topology 2A

®
Intel 852GM Chipset Platform Design Guide
CPU
VCCP
L2
L1
Rs
L2 L3 L4
VCCP
Rtt
L2
Intel Celeron M Processor Front Side Bus Design Guidelines
3.3
R1
Rtt
Q1
L3
3904
Rs R1
CPU
(System receiver)
3.3
V_IO_RCVR
R2
L4
Q2
3904
R2- Rtt
ICH4-M
L1
Transmission
Line Type
Micro-strip
Strip-line
67