Distance From Magnetics Module To Rj-45 (Distance A); Distance From Intel 82562Et To Magnetics Module (Distance B); Reducing Circuit Inductance - Intel 852GM Design Manual

I/O Subsystem

10.9.2.4.1. Distance from Magnetics Module to RJ-45 (Distance A)

The distance A in Figure 99 above should be given the highest priority in board layout. The distance
between the magnetics module and the RJ-45 connector should be kept to less than one inch of
separation. The following trace characteristics are important and should be observed:
• Differential Impedance: The differential impedance should be 100 Ω . The single ended trace
impedance will be approximately 50 Ω ; however, the differential impedance can also be affected by
the spacing between the traces.
• Trace Symmetry: Differential pairs (such as TDP and TDN) should be routed with consistent
separation and with exactly the same lengths and physical dimensions (for example, width).
Caution: Asymmetric and unequal length traces in the differential pairs contribute to common mode noise. This
can degrade the receive circuit's performance and contribute to radiated emissions from the transmit
circuit. If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector,
distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as
short as possible should be a priority.
Note: Measured trace impedance for layout designs targeting 100 Ω often result in lower actual impedance.
OEMs should verify actual trace impedance and adjust their layout accordingly. If the actual impedance
is consistently low, a target of 105 Ω to 110 Ω should compensate for second order effects.

10.9.2.4.2. Distance from Intel 82562ET to Magnetics Module (Distance B)

Distance B should also be designed to be less than one inch between devices. The high-speed nature of
the signals propagating through these traces requires that the distance between these components be
closely observed. In general, any section of traces that is intended for use with high-speed signals should
observe proper termination practices. Proper termination of signals can reduce reflections caused by
impedance mismatches between device and traces. The reflections of a signal may have a high
frequency component that may contribute more EMI than the original signal itself. For this reason, these
traces should be designed to a 100- Ω differential value. These traces should also be symmetric and equal
length within each differential pair.
10.9.2.5.

Reducing Circuit Inductance

The following guidelines show how to reduce circuit inductance in both back planes and motherboards.
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas
on a ground or power plane, the signal conductors should not cross the vacant area. This increases
inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog
signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems
such as analog to digital conversion, operational amplifiers, etc. All ground vias should be connected to
every ground plane; and similarly, every power via, to all power planes at equal potential. This helps
reduce circuit inductance. Another recommendation is to physically locate grounds to minimize the loop
area between a signal path and its return path. Rise and fall times should be as slow as possible because
signals with fast rise and fall times contain many high frequency harmonics that can radiate
significantly. The most sensitive signal returns closest to the chassis ground should be connected
186
Distance
A
B
Priority
1
2
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Intel 852GM Chipset Platform Design Guide
R
Guideline
< 1 inch
< 1 inch