Primary Ide Connector Requirements; Figure 73. Connection Requirements For Primary Ide Connector - Intel 852GM Design Manual

I/O Subsystem
10.1.2.

Primary IDE Connector Requirements

Figure 73. Connection Requirements for Primary IDE Connector

ICH4-M
† Due to ringing,
PCIRST# must be
buffered
• 22 Ω - 47 Ω series resistors are required on RESET#. The correct value should be determined for
each unique motherboard design, based on signal quality.
• An 8.2 k Ω - 10 k Ω pull-up resistor is required on IRQ14 to VCC3_3.
• A 4.7-k Ω, pull-up resistor to VCC3_3 is required on PIORDY.
• Series resistors can be placed on the control and data line to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
• The 10-k Ω resistor to ground on the PDIAG#/CBLID# signal is required on the Primary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the
IDE interface.
154
†
PCIRST#
3.3 V
4.7 k
PIORDY (PRDSTB / PWDMARDY#)
IRQ[14]
GPIOx
10 k
22 to 47 Ω
PDD[15:0]
PDA[2:0]
PDCS[3,1]#
PDIOR#
PDIOW#
PDDREQ
PDDACK#
8.2~10 k
PDIAG# / CBLID#
®
Intel 852GM Chipset Platform Design Guide
Primary IDE
3.3 V
CSEL
R