Processor System Bus Ac Specifications (Agtl+ Signal Group) At The Processor Core Pins (For Ppga Package); System Bus Ac Specifications (Agtl+ Signal Group) At The Processor Core Pins (For Fc-Pga/Fc-Pga2 Packages) - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for PPGA Package)
T7: AGTL+ Output Valid Delay
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are
All GTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor pins.
4. This specification applies to the processor operating with a 66 MHz system bus only.
5. Valid delay timings for these signals are specified into 25
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. After V
CC CORE
Table 16. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for FC-PGA/FC-PGA2 Packages)
T7: AGTL+ Output Valid Delay
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processors at all frequencies and
cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from V
rate of 0.3 V/ns.
8. Specification is for a maximum 1.0 V swing from V
9. This should be measured after V
10.This specification applies to the FC-PGA/FC-PGA2 packages running at 66 MHz system bus frequency.
11. This specification applies to the FC-PGA/FC-PGA2 packages running at 100 MHz system bus frequency.
40
T# Parameter
and BCLK become stable.
T# Parameter
CC CORE
Min Max Unit
0.30 4.43 ns
2.10 ns
0.85 ns
1.00 ms
erenced to the BCLK rising edge at 1.25 V at the processor pin.
REF
to 1.5 V and with V
Min Max Unit
0.40 3.25 ns
1.20 ns
1.00 ns
1.00 ms
to 1.5 V and with V
- 200 mV to V
REF
– 1V to V . This assumes an edge rate of 3 V/ns.
TT TT
, V , and BCLK become stable.
CC CMOS
Figure Notes
4 5
5 5, 6, 7
5
6 7, 8
at 1.0 V.
REF
Figure Notes
4 4, 10, 11
5 5, 6, 7, 10, 11
5 8, 10, 11
7 6, 9, 10, 11
at 1.0 V.
REF
+ 200 mV. This assumes an edge
REF
Datasheet