Topology 1A: Open Drain (Od) Signals Driven By The Processor - Ierr; Topology 1B: Open Drain (Od) Signals Driven By The Processor - Ferr# And Thermtrip; Figure 23. Routing Illustration For Topology 1A; Table 21. Layout Recommendations For Topology 1A - Intel 852GM Design Manual

R
5.5.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor
– IERR#
The Topology 1A OD signal IERR# should adhere to the following routing and layout
recommendations. Table 21 lists the recommended routing requirements for the IERR# signal of the
processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using
55 Ω ± 15% characteristic trace impedance. Series resistor R1 is a dampening resistor for reducing
overshoot/ undershoot reflections on the transmission line. The pull-up voltage for termination resistor
Rtt is VCCP (1.05 V). Due to the dependencies on system design implementation, IERR# can be
implemented in a number of ways to meet design goals. IERR# can be routed as a test point or to any
optional system receiver.

Figure 23. Routing Illustration for Topology 1A

Table 21. Layout Recommendations for Topology 1A

L1
0.5" – 12.0"
0.5" – 12.0"
5.5.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor
– FERR# and THERMTRIP#
The Topology 1B OD signals FERR# and THERMTRIP# should adhere to the following routing and
layout recommendations. Table 22 lists the recommended routing requirements for the FERR# and
THERMTRIP# signals of the processor. The routing guidelines allow the signals to be routed as either
micro-strips or strip-lines using 55 Ω ± 15% characteristic trace impedance. Series resistor R1 is a
dampening resistor for reducing overshoot/undershoot reflections on the transmission line. The pull-up
voltage for termination resistor Rtt is VCCP (1.05 V).
Intel recommends that the FERR# signal of the processor be routed to the FERR# signal of the ICH4-M.
THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the
ICH4-M or any optional system receiver. It is recommended that the THERMTRIP# signal of the
processor be routed to the THRMTRIP# signal of the ICH4-M. The ICH4-M's THRMTRIP# signal is a
new signal to the I/O controller hub architecture that allows the ICH4-M to quickly put the whole
system into a S5 state whenever the catastrophic thermal trip point has been reached.
®
Intel 852GM Chipset Platform Design Guide
Intel Celeron M Processor Front Side Bus Design Guidelines
CPU
L1
L2 L3
0" – 3.0" 0" – 3.0"
0" – 3.0" 0" – 3.0"
System
Receiver
L2
R1
L3
R1 Rtt
56 Ω ± 5% 56 Ω ± 5%
56 Ω ± 5% 56 Ω ± 5%
VCCP
Rtt
Transmission Line Type
Micro-strip
Strip-line
65