Emi Considerations; Common Mode Chokes; Figure 83. Good Downstream Power Connection; Figure 84. Common Mode Choke Schematic - Intel 852GM Design Manual

I/O Subsystem

Figure 83. Good Downstream Power Connection

10.4.4.

EMI Considerations

The following guidelines apply to the selection and placement of common-mode chokes and ESD
protection devices.
10.4.4.1.

Common Mode Chokes

Testing has shown that common-mode chokes can provide required noise attenuation. A design should
include a common-mode choke footprint to provide a stuffing option in the event the choke is needed to
pass EMI testing. Figure 84 shows the schematic of a typical common-mode choke and ESD
suppression components. The choke should be placed as close as possible to the USB connector signal
pins.

Figure 84. Common Mode Choke Schematic

Common mode chokes distort full-speed and high-speed signal quality. As the common mode
impedance increases, the distortion will increase, so you should test the effects of the common mode
choke on full speed and high-speed signal quality. Common mode chokes with a target impedance of
80 Ω to 90 Ω at 100 MHz generally provide adequate noise attenuation.
168
Thermister
5V
5V
Switc
5V
100-150uF
C om m on M ode
C hoke
D +
D -
E S D S upression
C om ponents
V V c c c c
1 1
470p
4 4
G G n n d d
V V c c c c
1 1
470p
4 4
G G n n d d
Vcc
®
Intel 852GM Chipset Platform Design Guide
R
Port1
Port2
U SB A
C onnector