Table of Contents
Advertisement
System Memory Design Guidelines (DDR-SDRAM)
7.3.5.5.
Control Group Package Length Table
The package length data in Table 40 below should be used to match the overall length of each command
signal to its associated clock reference length. Note that due to the relatively small variance in package
length and adequate timing margins it is acceptable to use a fixed 500-mil nominal package length for
all control signals, thereby reducing the complexity of the motherboard length calculations.
Table 40. Control Group Package Lengths
Signal
SCS#[0]
SCS#[1]
SCS#[2]
SCS#[3]
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
7.3.6.
Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#,
SWE#
The Intel 852GM GMCH chipset command signals, SMA[12:0], SBA[1:0], SRAS#, SCAS#, and SWE#
clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The GMCH drives the
command and clock signals together, with the clocks crossing in the valid command window. There are
two supported topologies for the command signal group, Topology 1, which is a daisy chain topology,
and Topology 2, which implements a T routing topology. Both topologies place a series resistor
between the two SO-DIMMs to dampen the SO-DIMM to SO-DIMM resonance. Topology 2 is the
topology that best allows for placement of the SO-DIMMs back to back in the butterfly configuration,
thus minimizing the SO-DIMM footprint area.
7.3.6.1.
Command Topology 1
The command signal routing should transition from an external layer to an internal signal layer under
the GMCH. Keep to the same internal layer until transitioning back to an external layer immediately
prior to connecting the SO-DIMM0 connector pad. At the via transition for SO-DIMM0, continue the
signal route on the same internal layer to the series termination resistor (Rs), connected to SO-DIMM1.
At this resistor the signal should transition to an external layer immediately prior to the pad of Rs. After
the series resistor, Rs, continue the signal route on the external layer landing on the appropriate
connector pad of SO-DIMM1. After SO-DIMM1, transition to the same internal layer or stay on the
external layer and route the signal to Rt.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
106
Pin Number
AD23
AD26
AC22
AC25
AC7
AB7
AC9
AC10
®
Intel
Package Length (mils)
502
659
544
612
443
389
386
376
852GM Chipset Platform Design Guide
R
Advertisement
Table of Contents
