Table of Contents
Advertisement
Platform Design Checklist
Figure 137. Mobile Intel Pentium 4 Processor-M Power Up Sequence
R ESET#
PW RG O O D
VID _G O O D
VID [4:0],
BSEL[1:0]
VCC VID
14.5.
Intel Celeron M Processor
14.5.1.
Resistor Recommendations
Pin Name
A20M#
BR0#
COMP0,
COMP2
COMP1,
COMP3
DPSLP#
FER#
GTLREF
244
BC LK
Vcc
Ta
Ta= 1us m inim um (VCC VID > 1V to VID _G O O D high)
Tb= 50m s m axim um (VID _G O O D to Vcc valid m axim um tim e)
Tc= T37 (PW R G O O D inactive pulse w idth)
Td= T36 (PW R G O O D to R ESET# de-assertion tim e)
N ote: VID_G O O D is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For m ore
inform ation on im plem entation refer to the Intel M obile Northwood
Processor and Intel 845M P Platform R DD P.
System
Series
Termination
Pull-up/Pull-
down
27.4 Ω ± 1%
pull-down to gnd
54.9 Ω ± 1%
pull-down to gnd
56 Ω pull-up to
56 Ω from pull-
VCCP
up to ICH4-M
pin.
1 K Ω ± 1% pull-
up to VCCP
2 K Ω ± 1% pull-
down to gnd
Tc
Tb
Voltage
Translation
Point-to-point connection to ICH4-M.
Point-to-point connection to GMCH.
Resistor placed within 0.5" of
processor pin. Trace should be 27.4 Ω
± 15%.
Resistor placed within 0.5" of
processor pin. Trace should be 55 Ω ±
15%.
Point-to-point connection to GMCH.
Point-to-point connection to ICH4-M,
with pull-up resistor and series resistor
placed by ICH4-M.
Voltage divider should be placed
within 0.5" of processor pin.
®
Intel
852GM Chipset Platform Design Guide
R
Td
Notes
Advertisement
Table of Contents
