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Intel 80960SA Manual

Embedded 32-bit microprocessor with 16-bit burst data bus
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Table of Contents
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
High-Performance Embedded
Architecture
— 20 MIPS* Burst Execution at 20 MHz
— 7.5 MIPS Sustained Execution
at 20 MHz
512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
The 80960SA is a member of Intel's i960
embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA
has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC
technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions
*
per second
. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including
non-impact printers, network adapters and I/O controllers.
SIXTEEN
32-BIT GLOBAL
REGISTERS
512-BYTE
INSTRUCTION
INSTRUCTION
FETCH UNIT
CACHE
Figure 1. The 80960SA Processor's Highly Parallel Architecture
* Relative to Digital Equipment Corporation's VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004
80960SA
Pin Compatible with 80960SB
Built-in Interrupt Controller
— 4 Direct Interrupt Pins
— 31 Priority Levels, 256 Vectors
Easy to Use, High Bandwidth 16-Bit Bus
— 32 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
32-Bit Address Space, 4 Gigabytes
80-Lead Quad Flat Pack (EIAJ QFP)
— 84-Lead Plastic Leaded Chip Carrier
Software Compatible with
80960KA/KB/CA/CF Processors
®
32-bit processor family, which is designed especially for low cost
64- BY 32-BIT
32-BIT
LOCAL
INSTRUCTION
REGISTER
EXECUTION
CACHE
UNIT
MICRO-
INSTRUCTION
INSTRUCTION
DECODER
SEQUENCER
August 2004
(PLCC)
32-BIT
BUS
CONTROL
MICRO-
LOGIC
INSTRUCTION
ROM
Order Number: 272206-003
32-BIT
ADDRESS
16-BIT
BURST
BUS

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  Summary of Contents for Intel 80960SA

  • Page 1 * Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment Corporation) Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
  • Page 2: Table Of Contents

    80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS CONTENTS PAGE ® 1.0 THE i960 PROCESSOR ...........................1 1.1 Key Performance Features .........................2 1.1.1 Memory Space And Addressing Modes ................... 4 1.1.2 Data Types ..........................4 1.1.3 Large Register Set ........................4 1.1.4 Multiple Register Sets ......................5 1.1.5 Instruction Cache ........................6...
  • Page 3 Capacitive Derating Curve ......................13 Figure 10 Test Load Circuit for Three-State Output Pins ................13 Figure 11 Drive Levels and Timing Relationships for 80960SA Signals ............. 15 Figure 12 Processor Clock Pulse (CLK2) ....................19 Figure 13 RESET Signal Timing ......................... 19 Figure 14 HOLD Timing ..........................
  • Page 5: The I960 ® Processor

    The 80960SA is a member of the 32-bit architecture from Intel known as the i960 processor family. These All members of the i960 processor family share a...
  • Page 6: Key Performance Features

    4. Simple Instruction Formats. All instructions in the 80960SA are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. To simplify the...
  • Page 7 80960SA Table 1. 80960SA Instruction Set Data Movement Arithmetic Logical Bit and Bit Field Load Set Bit Store Subtract Not And Clear Bit Move Multiply And Not Not Bit Load Address Divide Check Bit Remainder Exclusive Or Alter Bit Modulo...
  • Page 8: Memory Space And Addressing Modes

    8-, 16-, 32- and 64-bit ordinals bytes). • 8-, 16-, 32- and 64-bit integers For ease of use the 80960SA has a small number of Non-Numeric: addressing modes, but includes all those necessary to ensure efficient execution of high-level languages •...
  • Page 9: Multiple Register Sets

    If four or more procedures are active and a new 1.1.4 Multiple Register Sets procedure is called, the 80960SA moves the oldest local register set in the stack-frame cache to a To further increase the efficiency of the register set,...
  • Page 10: Instruction Cache

    One optimization method is the ability to overlap instructions by using register scoreboarding. The 80960SA can be interrupted in one of two ways: by the activation of one of four interrupt pins or by Register scoreboarding occurs when a LOAD moves sending a message on the processor’s data bus.
  • Page 11: 1.1.10 Fault Detection

    The breakpoint mechanism is easy to use and correctly. If a problem is discovered at any point provides a powerful debugging tool. during the self-test, the 80960SA asserts its FAIL pin and will not begin program execution. Self test takes Tracing is available for instructions (single step approximately 24,000 cycles to complete.
  • Page 12: Table 3 80960Sa Pin Description: Bus Signals

    DESCRIPTION CLK2 SYSTEM CLOCK provides the fundamental timing for 80960SA systems. It is divided by two inside the 80960SA to generate the internal processor clock. A31:16 ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory.
  • Page 13 80960SA Table 3. 80960SA Pin Description: Bus Signals (Sheet 2 of 2) NAME TYPE DESCRIPTION LOCK BUS LOCK prevents bus masters from gaining control of the bus during O.D. Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK.
  • Page 14: Table 4 80960Sa Pin Description: Support Signals

    80960SA Table 4. 80960SA Pin Description: Support Signals NAME TYPE DESCRIPTION RESET RESET clears the processor’s internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3, LOCK), the three-state output pins are placed in a HIGH impedance state (except for DT/R, DEN, and AS) and other output pins are placed in their non-asserted states.
  • Page 15: Electrical Specifications

    Figure 9 shows the typical capacitive derating curve recommended for best high frequency electrical for the 80960SA measured from 1.5V on the system performance. Inductance is reduced by shortening clock (CLK) to 0.8V on the falling edge and 2.0V on board traces between the processor and decoupling the rising edge of the bus address/data (AD) signals.
  • Page 16: Figure 6 Typical Supply Current Vs. Case Temperature

    80960SA = 5.0V 20 MHz 16 MHz 10 MHz 90 100 110 CASE TEMPERATURE (°C) Figure 6. Typical Supply Current vs. Case Temperature TEMP = +22°C 4.5V 5.0V 5.5V OPERATING FREQUENCY (MHz) Figure 7. Typical Current vs. Frequency (Room Temp)
  • Page 17: Test Load Circuit

    Figure 9. Capacitive Derating Curve (Hot Temp) Test Load Circuit Figure 10 illustrates the load circuit used to test the 80960SA’s output pins. THREE-STATE OUTPUT = 50 pF for all signals Figure 10. Test Load Circuit for Three-State Output Pins...
  • Page 18: Absolute Maximum Ratings

    “Operating Conditions” may affect device reliability. Voltage on Any Pin (QFP)....–0.25V to VCC +0.25V Power Dissipation ........1.9W (20 MHz) DC Characteristics 80960SA (10 and 16 MHz QFP) = 0°C to +100°C, V = 5V ± 5% CASE 80960SA (10 and 16 MHz PLCC) = 0°C to +85°C, V...
  • Page 19: Ac Specifications

    HLDA, LOCK, INTA 1.5V 1.5V 1.5V 1.5V VALID OUTPUT DT/R INPUTS: AD15:1, D0, 2.0V 2.0V INT0, INT1, 0.8V 0.8V INT2, INT3 VALID INPUT HOLD 2.0V 2.0V LOCK 0.8V 0.8V READY Figure 11. Drive Levels and Timing Relationships for 80960SA Signals...
  • Page 20: Table 6 80960Sa Ac Characteristics (10 Mhz)

    80960SA Table 6. 80960SA AC Characteristics (10 MHz) Symbol Parameter Units Notes Input Clock Processor Clock Period (CLK2) = 1.5V Processor Clock Low Time (CLK2) = 10% Point + (V – V ) x 0.1 Processor Clock High Time = 90% Point...
  • Page 21: Table 7 80960Sa Ac Characteristics (16 Mhz)

    80960SA Table 7. 80960SA AC Characteristics (16 MHz) Symbol Parameter Units Notes Input Clock Processor Clock Period (CLK2) 31.25 = 1.5V Processor Clock Low Time (CLK2) = 10% Point + (V – V ) x 0.1 Processor Clock High Time...
  • Page 22: Table 8 80960Sa Ac Characteristics (20 Mhz)

    80960SA Table 8. 80960SA AC Characteristics (20 MHz) Symbol Parameter Units Notes Input Clock Processor Clock Period (CLK2) = 1.5V Processor Clock Low Time (CLK2) = 10% Point + (V – V ) x 0.1 Processor Clock High Time (CLK2)
  • Page 23: Figure 12 Processor Clock Pulse (Clk2)

    80960SA HIGH LEVEL (MIN) 0.7V 1.5 V LOW LEVEL (MAX) 0.8V Figure 12. Processor Clock Pulse (CLK2) CLK2 OUTPUTS RESET INT0, INT1, INITIALIZATION PARAMETERS INT3, LOCK NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge.
  • Page 24: Figure 14 Hold Timing

    80960SA CLK2 HOLD HLDA Figure 14. HOLD Timing...
  • Page 25: Mechanical Data

    The QFP pins are numbered in order from 1 to 80 around the package perimeter. The PLCC pins are numbered in order from 1 to 84 around the package The 80960SA is available in two package types: perimeter. Tables 9 and 10 list the function of each •...
  • Page 26: Figure 16 84-Lead Plastic Leaded Chip Carrier (Plcc) Package

    80960SA 84 83 82 81 80 79 78 77 76 75 LOCK BLAST DT/R AD15 AD14 x80960SA-20 XXXXXXXX HOLD XXXXXX XXXXXX AD13 AD12 HLDA AD11 INT3/INTA AD10 INT2/INTR INT1 INT0 RESET CLK2 Figure 16. 84-Lead Plastic Leaded Chip Carrier (PLCC) Package NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
  • Page 27: Pinout

    80960SA Pinout Table 9. 80960SA QFP Pinout — In Pin Order Signal Signal Signal Signal CLK2 RESET INT0 INT1 READY INT2/INTR INT3/INTA AD15 HLDA AD14 HOLD AD13 AD12 AD11 DT/R AD10 BLAST LOCK NOTES: Do not connect any external logic to any pins marked NC.
  • Page 28: Table 10 80960Sa Qfp Pinout — In Signal Order

    80960SA Table 10. 80960SA QFP Pinout — In Signal Order Signal Signal Signal Signal DT/R HLDA HOLD INT0 INT1 INT2/INTR INT3/INTA LOCK AD10 READY AD11 RESET AD12 AD13 AD14 AD15 BLAST CLK2 NOTES: Do not connect any external logic to any pins marked N.C.
  • Page 29: Table 11 80960Sa Plcc Pinout — In Pin Order

    80960SA Table 11. 80960SA PLCC Pinout — In Pin Order Signal Signal Signal Signal HOLD AD13 AD12 AD11 DT/R AD10 BLAST LOCK CLK2 RESET INT0 INT1 READY INT2/INTR INT3/INTA AD15 HLDA AD14 NOTES: Do not connect any external logic to any pins marked NC.
  • Page 30: Table 12 80960Sa Plcc Pinout — In Signal Order

    80960SA Table 12. 80960SA PLCC Pinout — In Signal Order Signal Signal Signal Signal DT/R HLDA HOLD INT0 INT1 INT2/INTR INT3/INTA LOCK AD10 AD11 READY AD12 RESET AD13 AD14 AD15 BLAST AD16 CLK2 NOTES: Do not connect any external logic to any pins marked NC.
  • Page 31: Package Thermal Specifications

    (No Heatsink) θ Junction-to-Case NOTES: This table applies to 80960SA QFP soldered directly to board. Table 14. 80960SA PLCC Package Thermal Characteristics Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) Parameter 1000 θ...
  • Page 32: Waveforms

    80960SA WAVEFORMS Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SA’s bus. Figure 22 shows a cold reset functional waveform. CLK2 A31:16 VALID VALID A15:4, ADDR ADDR DATA D15:0 VALID INVALID VALID A3:1 BE1:0...
  • Page 33: Figure 18 Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States

    80960SA CLK2 VALID A31:16 A15:4, ADDR D15:0 A3:1 BE1:0 BLAST DT/R READY Figure 18. Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States...
  • Page 34: Figure 19 Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred)

    80960SA CLK2 VALID A31:16 A15:4, ADDR DATA DATA DATA DATA D15:0 A3:1 VALID VALID VALID VALID BE1:0 BLAST DT/R READY Figure 19. Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred)
  • Page 35: Figure 20 Accesses Generated By Quad Word Read Bus Request Misaligned One Byte From Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States

    80960SA Figure 20. Accesses Generated by Quad Word Read Bus Request, Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States...
  • Page 36: Figure 21 Interrupt Acknowledge Cycle

    80960SA CLK2 A31:16 A15:4, ADDR DATA D15:0 A3:1 1 1 0 BE1:0 INTA BLAST DT/R LOCK READY Figure 21. Interrupt Acknowledge Cycle...
  • Page 37 A B C D A B C D A B C D A B C D A B C D A B C D CLK2 AS, DT/R, DEN, LOCK (O) HLDA BLAST/FAIL ALE, A31:16, A15:4, A3:1, D15:0, BE1:0, W/R RESET INT0, INT1, VALID INT3,...
  • Page 38: Revision History

    -001 New section added. Data sheet 270917-004 applied to both the 80960SA and the 80960SB. The 80960SA was then documented alone in data sheet 272206-001. The sections significantly changed between revisions -004 of the SA/SB data sheet and 272206-001 of the SA data sheet were:...
  • Page 39 Pin Order (pg. 26) NOTES: Page numbers refer to 80960SA data sheet number 272206-001. The sections significantly changed between revisions -003 and -004 of the 80960SA/SB Data Sheet were: Last Section Description Rev.