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R
Voltage References, PLL Power Signals
• DVORCOMP
• GVREF
8.3.2.
DVO Port Interface Routing Guidelines
8.3.2.1.
Length Mismatch Requirements
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group, which are recommended to achieve optimal SI and timing. In addition to the absolute
length limits provided in the individual guideline tables, more restrictive length matching requirements
are also provided which further restrict the minimum to maximum length range of each signal group
with respect to clock strobe, within the overall boundaries defined in the guideline tables, as required to
guarantee adequate timing margins. Refer to Table 53 for DVO length matching requirements.
Table 53. DVO Interface Trace Length Mismatch Requirements
Data Group
DVOCD [11:0]
NOTES:
1. Data signals of the same group should be trace length matched to the clock within ±100 mil including package
lengths.
2. All length matching formulas are based on GMCH die-pad to DVO device pin total length. Package length
table are provided for all signals in order to facilitate this pad to pin matching.
8.3.2.2.
Package Length Compensation
As mentioned in Section 8.3.2.1, all length matching is done from GMCH die-pad to DVO connector
pin. The reason for this is to compensate for the package length variation across each signal group in
order to minimize timing variance. The GMCH does not equalize package lengths internally as some
previous GMCH components have, and therefore, the GMCH requires a length matching process. See
Table 55 for DVOC package lengths information.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the minimum and maximum length bounds of a signal
group based on clock length, whereas package length compensation refers to the process of adjusting
out package length variance across a signal group. There is of course some overlap in that both affect
the target length of an individual signal. Intel recommends that the initial route be completed based on
the length matching formulas in conjunction with nominal package lengths and that package length
compensation is performed as a secondary operation.
®
Intel
852GM Chipset Platform Design Guide
Signal Matching to
DVO Clock Strobes
Strobe Clock
Associated With the Group
± 100 mils
Integrated Graphics Display Port
Clock Strobe Matching
DVOCCLK[1:0]
Notes
± 10 mils
1,2
139
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