Itp Debug Port; Figure 16. Routing Illustration For Topology 3; Figure 17. Voltage Translation Circuit For 3.3-V Receivers; Table 11. Layout Recommendations For Topology 3 - Intel 852GM Design Manual

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
R

Figure 16. Routing Illustration for Topology 3

Table 11. Layout Recommendations for Topology 3

L1 + L2
0.5" – 12.0"
0.5" – 12.0"

Figure 17. Voltage Translation Circuit for 3.3-V Receivers

4.4.

ITP Debug Port

Please refer to the ITP700 Debug Port Design Guide, which can be found on
http://developer.intel.com/design/Xeon/guides/249679.htm.
Note: This change is effective for all future processors and includes information on both ITP700 and ITP700
Flex.
®
Intel 852GM Chipset Platform Design Guide
CPU ICH4-M
L1
L2
Rs
L3 L4
300 Ω ± 5%
0" – 3.0" 0.5" – 6.0"
300 Ω ± 5%
0" – 3.0" 0.5" – 6.0"
1.3K ohm
+/- 5%
330 ohm
+/- 5%
From Driver
Rs
3.3V
R1
Q2
Q1
L3
3904
Rs R1
2k Ω ± 5%
2k Ω ± 5%
3.3V
3.3V
330 ohm
+/- 5%
R1
Q2
3904
Q1
3904
FWH
3.3V
V_IO_FWH
R2
L4
3904
R2 Transmission Line
Type
300 Ω ± 5%
Micro-strip
300 Ω ± 5%
Strip-line
R2
To Receiver
45