Table of Contents
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A
7,13,14
4
7,13,14
7,13,14
7,11,14
7,13,14
7,13,14
11,13,14
M_CKE0, M_CKE1, M_CS0#, M_CS1#
are only for LAI support.
3
7,14
7,14
7,13,14
7,13,14
7,13,14
11
+V3.3S_SPD
7,14
7,14
6,8,11,16,18
6,8,11,16,18
11,13,14
2
11,13,14
1
A
B
M_AA0
J6H2ACON200_DDR-SODIMM_REV
M_AA0
M_AB1
112
A0
M_AB2
111
7,14
M_AB[2:1]
A1
110
A2
M_AA3
109
A3
M_AA3
M_AB4
108
A4
M_AB5
107
7,14
M_AB[5:4]
A5
M_AA6
106
A6
M_AA7
105
M_AA[12:6]
A7
M_AA8
102
A8
M_AA9
101
A9
M_AA10
115
A10/AP
M_AA11
100
A11
M_AA12
99
A12
97
A13(DU)
M_CS0#
117
M_BS0#
BA0
116
M_BS1#
BA1
98
M_CB_R[7:0]
BA2(DU)
M_CB_R0
71
CB0
M_CB_R1
73
CB1
M_CB_R2
79
CB2
M_CB_R3
83
CB3
M_CB_R4
72
CB4
M_CB_R5
74
CB5
M_CB_R6
80
CB6
M_CB_R7
84
CB7
35
7
M_CLK_DDR3
CK0
37
7
M_CLK_DDR3#
CK0#
158
7
M_CLK_DDR4#
CK1#
160
7
M_CLK_DDR4
CK1
89
7
M_CLK_DDR5
CK2
91
7
M_CLK_DDR5#
CK2#
96
M_CKE2
CKE0
95
M_CKE3
CKE1
120
M_CAS#
CAS#
118
M_RAS#
RAS#
119
M_WE#
WE#
121
M_CS2#
S0#
122
M_CS3#
S1#
194
SA0
196
SA1
198
SA2
195
SMB_CLK_S
SCL
193
SMB_DATA_S
SDA
86
7,11,14
M_CKE0
RESET(DU)
M_DM_R_[8:0]
M_DM_R_0
12
DM0
M_DM_R_1
26
DM1
M_DM_R_2
48
DM2
M_DM_R_3
62
DM3
M_DM_R_4
134
DM4
M_DM_R_5
148
DM5
M_DM_R_6
170
DM6
M_DM_R_7
184
DM7
M_DM_R_8
78
DM8
M_DQS_R[8:0]
M_DQS_R0
11
DQS0
M_DQS_R1
25
DQS1
M_DQS_R2
47
DQS2
M_DQS_R3
61
DQS3
M_DQS_R4
133
DQS4
M_DQS_R5
147
DQS5
M_DQS_R6
169
DQS6
M_DQS_R7
183
DQS7
M_DQS_R8
77
DQS8
SO-DIMM 1
SO-DIMM 1 is placed farther from
the GMCH than SO-DIMM 0
B
C
11,13,14
M_DATA_R_[63:0]
M_DATA_R_0
5
DQ0
M_DATA_R_1
7
DQ1
M_DATA_R_2
13
DQ2
M_DATA_R_3
17
DQ3
M_DATA_R_4
6
DQ4
M_DATA_R_5
8
DQ5
M_DATA_R_6
14
DQ6
M_DATA_R_7
18
DQ7
M_DATA_R_8
19
DQ8
M_DATA_R_9
23
DQ9
M_DATA_R_10
29
DQ10
M_DATA_R_11
31
DQ11
M_DATA_R_12
20
DQ12
M_DATA_R_13
24
DQ13
M_DATA_R_14
30
DQ14
M_DATA_R_15
32
DQ15
M_DATA_R_16
41
DQ16
M_DATA_R_17
43
DQ17
M_DATA_R_18
49
DQ18
M_DATA_R_19
53
DQ19
M_DATA_R_20
42
DQ20
M_DATA_R_21
44
DQ21
M_DATA_R_22
50
DQ22
M_DATA_R_23
54
DQ23
M_DATA_R_24
55
DQ24
M_DATA_R_25
59
DQ25
M_DATA_R_26
65
DQ26
M_DATA_R_27
67
DQ27
M_DATA_R_28
56
DQ28
M_DATA_R_29
60
DQ29
M_DATA_R_30
66
DQ30
M_DATA_R_31
68
DQ31
M_DATA_R_32
127
DQ32
M_DATA_R_33
129
DQ33
M_DATA_R_34
135
DQ34
M_DATA_R_35
139
DQ35
M_DATA_R_36
128
DQ36
M_DATA_R_37
130
DQ37
11,44
SM_VREF_DIMM
M_DATA_R_38
136
DQ38
M_DATA_R_39
140
DQ39
M_DATA_R_40
141
DQ40
M_DATA_R_41
145
DQ41
M_DATA_R_42
151
DQ42
M_DATA_R_43
153
DQ43
M_DATA_R_44
142
DQ44
M_DATA_R_45
146
DQ45
M_DATA_R_46
152
DQ46
M_DATA_R_47
154
DQ47
M_DATA_R_48
163
DQ48
M_DATA_R_49
165
DQ49
M_DATA_R_50
171
DQ50
M_DATA_R_51
175
DQ51
M_DATA_R_52
164
DQ52
M_DATA_R_53
166
DQ53
M_DATA_R_54
172
DQ54
M_DATA_R_55
176
DQ55
M_DATA_R_56
177
DQ56
M_DATA_R_57
181
DQ57
M_DATA_R_58
187
DQ58
M_DATA_R_59
189
DQ59
M_DATA_R_60
178
DQ60
M_DATA_R_61
182
DQ61
M_DATA_R_62
188
DQ62
M_DATA_R_63
190
DQ63
C
D
11,44,46,51
+V2.5_DDR
J6H2B CON200_DDR-SODIMM_REV
9
VDD1
VSS1
21
VDD2
VSS2
33
VDD3
VSS3
45
VDD4
VSS4
57
VDD5
VSS5
69
VDD6
VSS6
81
VDD7
VSS7
93
VDD8
VSS8
113
VDD9
VSS9
131
VDD10
VSS10
143
VDD11
VSS11
155
VDD12
VSS12
157
VDD13
VSS13
167
VDD14
VSS14
179
VDD15
VSS15
191
VDD16
VSS16
10
VDD17
VSS17
22
VDD18
VSS18
34
VDD19
VSS19
36
VDD20
VSS20
46
VDD21
VSS21
58
VDD22
VSS22
70
VDD23
VSS23
82
VDD24
VSS24
92
VDD25
VSS25
94
VDD26
VSS26
114
VDD27
VSS27
132
VDD28
VSS28
144
VDD29
VSS29
156
VDD30
VSS30
11
+V3.3S_SPD
168
VDD31
VSS31
180
VDD32
VSS32
192
VDD33
VSS33
199
VDDID
DU1
197
VDDSPD
DU2
1
VREF1
DU3
2
VREF2
DU4
C6W6
GND0
0.1UF
GND1
+V2.5_DDR
11,44,46,51
C6H2
C6G2
C5V2
C4V1
150uF
150uF
0.1UF
0.1UF
C5V3
C6V1
C5V1
C5W1
0.1UF
0.1UF
0.1UF
0.1UF
Layout note: Place capacitors between and near DDR connectors if possible.
Title
DDR SO-DIMMs (2 of 2)
Size
Project:
A
Intel Celeron M / 852GM CRB C26116
Date:
Wednesday, January 12, 2005
D
E
4
3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
3
88
90
104
126
138
150
162
174
186
85
M_CKE1
7,11,14
123
SO-DIMM_RSVD
124
M_CS1#
7,11,14
200
201
202
9,11,44
+V2.5
2
R4V1
0.01_1%
C4W1
C6W1
0.1UF
0.1UF
C5W2
0.1UF
1
Document Number
Rev
4.403
Sheet
12
of
51
E
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