Table of Contents
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A
4
13
M_AA_FR_0
7,14
M_AA[2:1]
13
M_AA_FR_3
7,14
M_AA[5:4]
13
M_AA_FR_[12:6]
13
M_BS0_FR#
13
M_BS1_FR#
12..14
M_CB_R[7:0]
3
7
M_CLK_DDR0
7
M_CLK_DDR0#
7
M_CLK_DDR1#
7
M_CLK_DDR1
7
M_CLK_DDR2
7
M_CLK_DDR2#
7,12,14
M_CKE0
7,12,14
M_CKE1
13
M_CAS_FR#
13
M_RAS_FR#
13
M_WE_FR#
7,12,14
M_CS0#
7,12,14
M_CS1#
6,8,12,16,18
SMB_CLK_S
6,8,12,16,18
SMB_DATA_S
12..14
M_DM_R_[8:0]
2
12..14
M_DQS_R[8:0]
1
A
B
12..14
M_DATA_R_[63:0]
M_AA_FR_0
J6H1A CON200_DDR-SODIMM
M_AA1
112
5
A0
DQ0
M_AA2
111
7
A1
DQ1
110
13
A2
DQ2
M_AA_FR_3
109
17
A3
DQ3
M_AA4
108
6
A4
DQ4
M_AA5
107
8
A5
DQ5
M_AA_FR_6
106
14
A6
DQ6
M_AA_FR_7
105
18
A7
DQ7
M_AA_FR_8
102
19
A8
DQ8
M_AA_FR_9
101
23
A9
DQ9
M_AA_FR_10
115
29
A10/AP
DQ10
M_AA_FR_11
100
31
A11
DQ11
M_AA_FR_12
99
20
A12
DQ12
97
24
A13(DU)
DQ13
30
DQ14
117
32
BA0
DQ15
116
41
BA1
DQ16
98
43
BA2(DU)
DQ17
M_CB_R0
71
49
CB0
DQ18
M_CB_R1
73
53
CB1
DQ19
M_CB_R2
79
42
CB2
DQ20
M_CB_R3
83
44
CB3
DQ21
M_CB_R4
72
50
CB4
DQ22
M_CB_R5
74
54
CB5
DQ23
M_CB_R6
80
55
CB6
DQ24
M_CB_R7
84
59
CB7
DQ25
35
65
CK0
DQ26
37
67
CK0#
DQ27
158
56
CK1#
DQ28
160
60
CK1
DQ29
89
66
CK2
DQ30
91
68
CK2#
DQ31
96
127
CKE0
DQ32
95
129
CKE1
DQ33
120
135
CAS#
DQ34
118
139
RAS#
DQ35
119
128
WE#
DQ36
121
130
S0#
DQ37
122
136
S1#
DQ38
194
140
SA0
DQ39
196
141
SA1
DQ40
198
145
SA2
DQ41
195
151
SCL
DQ42
193
153
SDA
DQ43
86
142
RESET(DU)
DQ44
146
DQ45
M_DM_R_0
12
152
DM0
DQ46
M_DM_R_1
26
154
DM1
DQ47
M_DM_R_2
48
163
DM2
DQ48
M_DM_R_3
62
165
DM3
DQ49
M_DM_R_4
134
171
DM4
DQ50
M_DM_R_5
148
175
DM5
DQ51
M_DM_R_6
170
164
DM6
DQ52
M_DM_R_7
184
166
DM7
DQ53
M_DM_R_8
78
172
DM8
DQ54
176
DQ55
M_DQS_R0
11
177
DQS0
DQ56
M_DQS_R1
25
181
DQS1
DQ57
M_DQS_R2
47
187
DQS2
DQ58
M_DQS_R3
61
189
DQS3
DQ59
M_DQS_R4
133
178
DQS4
DQ60
M_DQS_R5
147
182
DQS5
DQ61
M_DQS_R6
169
188
DQS6
DQ62
M_DQS_R7
183
190
DQS7
DQ63
M_DQS_R8
77
DQS8
SO-DIMM 0
B
C
3,5,6,8,9,15..18,20,21,23,26,31,33..36,38..40,43,45,51
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
12,44
SM_VREF_DIMM
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
C
D
+V3.3S
R4W1
Power plane for Serial Presence Detect logic
12,44,46,51
+V2.5_DDR
J6H1B CON200_DDR-SODIMM
9
VDD1
VSS1
21
VDD2
VSS2
33
VDD3
VSS3
45
VDD4
VSS4
57
VDD5
VSS5
69
VDD6
VSS6
81
VDD7
VSS7
93
VDD8
VSS8
113
VDD9
VSS9
131
VDD10
VSS10
143
VDD11
VSS11
155
VDD12
VSS12
157
VDD13
VSS13
167
VDD14
VSS14
179
VDD15
VSS15
191
VDD16
VSS16
10
VDD17
VSS17
22
VDD18
VSS18
34
VDD19
VSS19
36
VDD20
VSS20
46
VDD21
VSS21
58
VDD22
VSS22
70
VDD23
VSS23
82
VDD24
VSS24
92
VDD25
VSS25
94
VDD26
VSS26
114
VDD27
VSS27
132
VDD28
VSS28
144
VDD29
VSS29
156
VDD30
VSS30
12
+V3.3S_SPD
168
VDD31
VSS31
180
VDD32
VSS32
192
VDD33
VSS33
199
VDDID
DU1
197
VDDSPD
DU2
1
VREF1
DU3
2
VREF2
DU4
C6V2
GND0
0.1UF
GND1
+V2.5_DDR
12,44,46,51
C4G1
C4G2
C6W2
C4W2
150uF
150uF
0.1UF
0.1UF
C6W8
C5W3
C5W5
C5W4
0.1UF
0.1UF
0.1UF
0.1UF
Layout note: Place capacitors between and near DDR connector if possible.
Title
DDR SO-DIMMs (1 of 2)
Size
Project:
A
Intel Celeron M / 852GM CRB C26116
Date:
Wednesday, January 12, 2005
D
E
12
+V3.3S_SPD
0.01_1%
4
3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
3
64
76
88
90
104
126
138
150
162
174
186
85
123
SO-DIMM_RSVD_FR
124
200
201
202
2
9,12,44
+V2.5
R4F1
0.01_1%
C4W3
0.1UF
C5W6
0.1UF
1
Document Number
Rev
4.403
Sheet
11
of
51
E
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