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R
7.3.6.4.
Command Topology 2
The command signal routing should transition from an external layer to an internal signal layer under
the GMCH. Keep to the same internal layer until transitioning back to an external layer at the series
resistor Rs. At this point there is a T in the topology. One leg of the T will route through Rs and either
transition back to the same internal layer or stay external and landing on the appropriate connector pad
of SO-DIMM0. If it was necessary to return to the internal layer the signal should return to the external
layer immediately prior to landing on the appropriate connector pad of SO-DIMM0. The other leg of the
T will continue on the same internal layer and return to the external layer immediately prior to landing
on the appropriate connector pad of SO-DIMM1. If possible stay on the external layer and connect to
the parallel termination resistor or if the parallel termination resistor is on the opposite side of the board
from the SO-DIMM1 connector then share the via and route to the parallel termination resistor. If
sharing the via or using the opposite side of the board is not possible, continue on the same internal layer
and route to the external layer immediately prior to the termination resistor.
External trace lengths should be minimized. It is suggested that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. It is recommended that
command signal group be routed on same internal layer.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can not be placed within the same R-packs as data, strobe or control signals. Figure 55 and Table
42 below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.
Figure 55. Command Routing Topology 2
GMCH
GMCH
Pin
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-
DDR related signals. Command signals should be routed on inner layers with minimized external trace
lengths.
®
Intel
852GM Chipset Platform Design Guide
L1
P1
SO-DIMM0 PAD
System Memory Design Guidelines (DDR-SDRAM)
L3
Rs
SO-DIMM1 PAD
L2
Vtt
Rt
L4
111
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