Table of Contents
Advertisement
R
at higher frequencies and will degrade the transmit BER performance. Caution should be
exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be
less than 22 pF. (6 pF to 12 pF values have been used on past designs with reasonably good
success.) These caps are not necessary, unless there is some overshoot in 100-Mbps mode.
Note: It is important to keep the two traces within a differential pair close
helps to make them more immune to crosstalk and other sources of common-mode noise. This also
means lower emissions (i.e. FCC compliance) from the transmit traces, and better receive BER for the
receive traces.
†
Close should be considered to be less than 0.030 inches between the two traces within a differential
pair. 0.007 inch trace-to-trace spacing is recommended.
10.10.
Power Management Interface
10.10.1. SYS_RESET# Usage Model
The System Reset signal (SYS_RESET#) of the ICH4-M can be connected directly to a reset button or
any other equivalent driver in the system where the desired effect is to immediately put the system into
reset. A weak pull-up resistor pulled-up to the 3.3-V standby rail (VccSUS3_3) should be implemented
to ensure that no potential floating inputs to SYS_RESET# cause a system reset. The ICH4-M will
debounce signals on this pin (16 ms) and allow the SMBus to go idle before resetting the system. This
delay to allow all outstanding SMBus cycles to complete first is to prevent a slave device on the SMBus
from "hanging" by resetting in the middle of a SMBus cycle.
10.10.2. PWRBTN# Usage Model
The Power Button signal (PWRBTN#) of the ICH4-M can be connected directly to a power button or
any other equivalent driver (e.g. power management controller) where the desired effect is to indicate a
system request to go to a sleep state (if in a normal operating mode) or to cause a wake event (if in a
sleep state already). This signal is internally pulled-up in the ICH4-M to the 3.3-V standby rail
(VccSUS3_3) through a weak pull-up resistor (24 k Ω nominal). The ICH4-M has 16 ms of internal
debounce logic on this pin.
10.10.3. Power Well Isolation Control Strap Requirements
The circuit shown in the figure below can be implemented to control well isolation between the
VccSUS3_3 and RTC power wells in the event that RSMRST# is not being actively asserted during the
discharge of the standby rail. Failure to implement this circuit or a circuit which functions similar to this
may result in excessive droop on the VccRTC node during Sx-to-G3 power state transitions (removal of
AC power and battery power). Droop on this node can potentially cause the CMOS to be cleared or
corrupted, the RTC to lose time after several AC/battery power cycles, or the intruder bit might assert
erroneously.
®
Intel
852GM Chipset Platform Design Guide
I/O Subsystem
†
to each other. Keeping them close
†
193
Advertisement
Table of Contents
