Single Ended Host Bus Clocking Routing; Host Bus Clock Connections - Intel Pentium III Design Manual

Figure 4-1. Host Bus Clock Connections
Clock
Driver
The clocking requirements and timing information for the Intel
Cache can be found in the Intel
information about the timing and clocking requirements of the chipset component, please contact your
chipset vendor for the appropriate documentation.
4.2

Single Ended Host Bus Clocking Routing

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Intel Pentium III Processor with 512KB L2 Cache dual-processor platforms have support for using
single-ended host bus clock drivers. When using this clocking method, the BCLK signal (pin W37) is
used as the single-ended clock input to the processor. The BCLK#/CLKREF signal (pin Y33) is used as a
reference voltage and must be connected to the appropriate filter circuit described in
Figure 4-2 shows the topology that should be used for the processor clock traces. Please note that L0,
L1, and L2 refer to trace lengths between the illustrated components.
recommended lengths and component values for this topology.
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4-2 Intel Pentium
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Pentium III Processor with 512KB L2 Cache Datasheet. For additional
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
Debug
port
® ®
Pentium III Processor with 512KB L2
Table 4-1
Processor 0
Processor 1
Chipset
Section 4.2.1.
contains the