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20.9.2.1.22 USB0 Mode Register (USB0MODE)
The USB0 mode register (USB0MODE) supports operating the PHY in a non-OTG mode. This requires
the user to set the MGC UTMI input signal iddig. OTG interfaces have an id external pin which control
UTMI signal iddig. Since this external pin is not available, the user should set iddig to either a 0 (A-type)
or 1 (B-type). This value will be the initial setting for the Mentor controller. But, the controller will
determine whether it is operating as a host or device via its protocols. To determine the function of the
controller this information can be found by reading the Mentor Controller DEVCTL register (0x80) bit 2.
The loopback bit enables the loopback test. This test allows MGC0 to be connected to MGC1. It is
important to set both loopback bits in both USB0/1 Mode registers. The USB0 MGC UTMI loopback
register contains the various UTMI signals to be controlled and observed during loopback test.
The phy_test bit enables the phy_test mode. This test mode is intended to allow additional control of
the UTMI inputs to the PHY. Currently, these inputs are drvvbus, dppulldown, dmpulldown, and
idpullup. When phy_test is high, then the pin inputs for these signals control the inputs to the PHY
instead of the Mentor controller outputs. The phy_test mode is not active with loopback mode is active.
When phy_test is active than the PHY inputs datainh is equal to datain. And txvalidh is equal to txvalid.
The USB0 mode register is shown in
31
15
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-97. USB0 Mode Register (USB0MODE) Field Descriptions
Bits
Field
31-9
Reserved
8
iddig
7-2
Reserved
1
phy_test
0
loopback
20.9.2.1.23 USB0 Mentor Core Registers
A description of the Mentor core registers is available in
core exists, USB0 and USB1. These registers reside back to back within USB0 space. The core
registers that are used by USB0 subsystem are defined within offsets 1400h-159Ch, while the core
registers that are used by USB1 subsystem are defined within offset 1C00h-1D9Ch.
SPRUGX9 – 15 April 2011
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Preliminary
Figure 20-86
and described in
Figure 20-86. USB0 Mode Register (USB0MODE)
Reserved
R-0h
9
8
iddig
R/W-0h
Value
Description
0
Always read as 0. Writes have no effect.
MGC input value for iddig
0
A type
1
B type
0
Always read as 0. Writes have no effect.
PHY test
0
Normal mode
1
PHY test mode
Loopback test mode
0
Normal mode
1
Loopback test mode
© 2011, Texas Instruments Incorporated
Table
20-97.
7
2
Reserved
R-0h
Section
20.9.6. Two instantiations of the USB
Universal Serial Bus (USB)
Registers
16
1
0
phy_test
loopback
R/W-0h
R/W-0h
1885
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