Supplementary Control Register (Scr); Supplementary Control Register (Scr) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

19.3.27 Supplementary Control Register (SCR)

The supplementary control register (SCR) is shown in
NOTE: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the IIR register.
Therefore, when an interrupt occurs and there is no interrupt pending in the IIR register,
the SSR[1] bit must be checked. To clear the wake-up interrupt, bit SCR[4] must be reset
to 0.
15
7 6
RXTRIGGRANU1 TXTRIGGRANU1
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-38. Supplementary Control Register (SCR) Field Descriptions
Bit Field
15-8 Reserved
7 RXTRIGGRANU1
6 TXTRIGGRANU1
5 DSRIT
4 RXCTSDSRWAKEUPENABLE
3 TXEMPTYCTLIT
2-1 DMAMODE2
0 DMAMODECTL
1736
UART/IrDA/CIR Module
Preliminary
Figure 19-54. Supplementary Control Register (SCR)
Reserved
5 4
DSRIT RXCTSDSRWAKEUPENABLE
R/W-0 R/W-0
Value Description
0 Reserved.
0 Disables the granularity of 1 for trigger RX level.
1 Enables the granularity of 1 for trigger RX level.
0 Disables the granularity of 1 for trigger TX level.
1 Enables the granularity of 1 for trigger TX level.
0 Disables DSR interrupt.
1 Enables DSR interrupt.
RX CTS wake-up enable.
0 Disables the WAKE UP interrupt and clears SSR[1].
1 Waits for a falling edge of RX, CTS, or DSR pins to generate an interrupt.
0 Normal mode for THR interrupt.
1 THR interrupt is generated when TX FIFO and TX shift register are empty.
0-3h Specifies the DMA mode valid if SCR[0] = 1:
0 DMA mode 0 (no DMA).
1h DMA mode 1 (UARTnDMAREQ[0] in TX, UARTnDMAREQ[1] in RX)
2h DMA mode 2 (UARTnDMAREQ[0] in RX)
3h DMA mode 3 (UARTnDMAREQ[0] in TX)
0 The DMAMODE is set with FCR[3].
1 The DMAMODE is set with SCR[2:1].
© 2011, Texas Instruments Incorporated
Figure 19-54 and described in
R-0
3 2
TXEMPTYCTLIT
R/W-0
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Table 19-38.
8
1 0
DMAMODE2 DMAMODECTL
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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