Usbss Irq_Dma_Threshold_Rx1_3 Register (Irqdmatholdrx13); Usbss Irq_Dma_Threshold_Rx1_3 Register (Irqdmatholdrx13) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
Table of Contents

Advertisement

Registers

20.9.1.23 USBSS IRQ_DMA_THRESHOLD_RX1_3 Register (IRQDMATHOLDRX13)

The USBSS IRQ_DMA_THRESHOLD_RX1_3 register (IRQDMATHOLDRX13) defines the size of the
four DMA thresholds for interrupt pacing for USB1. Each threshold contains an 8-bit unsigned number
and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific endpoint
has exceeded the value of the threshold. The counter for the compared value is also an 8-bit unsigned
number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_DMA_THRESHOLD_RX1_3 register is shown in
Table
20-54.
Figure 20-44. USBSS IRQ_DMA_THRESHOLD_RX1_3 Register (IRQDMATHOLDRX13)
31
dma_thres_rx1_15
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-54. USBSS IRQ_DMA_THRESHOLD_RX1_3 Register (IRQDMATHOLDRX13) Field
Bits
Field
31-24
dma_thres_rx1_15
23-16
dma_thres_rx1_14
15-8
dma_thres_rx1_13
7-0
dma_thres_rx1_12
1844
Universal Serial Bus (USB)
24 23
dma_thres_rx1_14
R/W-0
Description
DMA threshold value for rx_pkt_cmp_0 for USB1 endpoint 15.
DMA threshold value for rx_pkt_cmp_0 for USB1 endpoint 14.
DMA threshold value for rx_pkt_cmp_0 for USB1 endpoint 13.
DMA threshold value for rx_pkt_cmp_0 for USB1 endpoint 12.
© 2011, Texas Instruments Incorporated
Preliminary
Figure 20-44
16 15
dma_thres_rx1_13
R/W-0
Descriptions
www.ti.com
and described in
8
7
dma_thres_rx1_12
R/W-0
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
0

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TMS320C6A816 Series and is the answer not in the manual?

Subscribe to Our Youtube Channel

Table of Contents