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Registers
20.9.1.8 USBSS IRQ_DMA_THRESHOLD_TX0_0 Register (IRQDMATHOLDTX00)
The USBSS IRQ_DMA_THRESHOLD_TX0_0 register (IRQDMATHOLDTX00) defines the size of the
four DMA thresholds for interrupt pacing for USB0. Each threshold contains an 8-bit unsigned number
and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific endpoint
has exceeded the value of the threshold. The counter for the compared value is also an 8-bit unsigned
number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_DMA_THRESHOLD_TX0_0 register is shown in
Table
20-39.
Figure 20-29. USBSS IRQ_DMA_THRESHOLD_TX0_0 Register (IRQDMATHOLDTX00)
31
dma_thres_tx0_3
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-39. USBSS IRQ_DMA_THRESHOLD_TX0_0 Register (IRQDMATHOLDTX00) Field
Bits
Field
31-24
dma_thres_tx0_3
23-16
dma_thres_tx0_2
15-8
dma_thres_tx0_1
7-0
Reserved
1836
Universal Serial Bus (USB)
24 23
dma_thres_tx0_2
R/W-0
Description
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 3.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 2.
DMA threshold value for tx_pkt_cmp_0 for USB0 v 1.
Always read as 0. Writes have no effect.
© 2011, Texas Instruments Incorporated
Preliminary
Figure 20-29
16 15
dma_thres_tx0_1
R/W-0
Descriptions
www.ti.com
and described in
8
7
Reserved
R-0
SPRUGX9 – 15 April 2011
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