Usbss Irq_Frame_Threshold_Rx0_2 Register (Irqframetholdrx02); Usbss Irq_Frame_Threshold_Rx0_3 Register (Irqframetholdrx03); Usbss Irq_Frame_Threshold_Rx0_2 Register (Irqframetholdrx02) Field Descriptions; Usbss Irq_Frame_Threshold_Rx0_3 Register (Irqframetholdrx03) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

20.9.1.32 USBSS IRQ_FRAME_THRESHOLD_RX0_2 Register (IRQFRAMETHOLDRX02)

The USBSS IRQ_FRAME_THRESHOLD_RX0_2 register (IRQFRAMETHOLDRX02) defines the size of
the four FRAME thresholds for interrupt pacing for USB0. Each threshold contains is an 8-bit unsigned
number and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific
endpoint has exceeded the value of the threshold. The counter for the compared value is also an 8-bit
unsigned number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_FRAME_THRESHOLD_RX0_2 register is shown in
Table 20-63.
Figure 20-53. USBSS IRQ_FRAME_THRESHOLD_RX0_2 Register (IRQFRAMETHOLDRX02)
31
frame_thres_rx1_11
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-63. USBSS IRQ_FRAME_THRESHOLD_RX0_2 Register (IRQFRAMETHOLDRX02) Field
Bits Field
31-24 frame_thres_rx1_11
23-16 frame_thres_rx1_10
15-8 frame_thres_rx1_9
7-0 frame_thres_rx1_8

20.9.1.33 USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register (IRQFRAMETHOLDRX03)

The USBSS IRQ_FRAME_THRESHOLD_RX0_3 register (IRQFRAMETHOLDRX03) defines the size of
the four FRAME thresholds for interrupt pacing for USB0. Each threshold contains is an 8-bit unsigned
number and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific
endpoint has exceeded the value of the threshold. The counter for the compared value is also an 8-bit
unsigned number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_FRAME_THRESHOLD_RX0_3 register is shown in
Table 20-64.
Figure 20-54. USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register (IRQFRAMETHOLDRX03)
31
frame_thres_rx1_15
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-64. USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register (IRQFRAMETHOLDRX03) Field
Bits Field
31-24 frame_thres_rx1_15
23-16 frame_thres_rx1_14
15-8 frame_thres_rx1_13
7-0 frame_thres_rx1_12
1850
Universal Serial Bus (USB)
24 23
frame_thres_rx1_10
R/W-0
Description
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 11.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 10.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 9.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 8.
24 23
frame_thres_rx1_14
R/W-0
Description
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 15.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 14.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 13.
FRAME threshold value for rx_pkt_cmp_0 for USB1 endpoint 12.
© 2011, Texas Instruments Incorporated
Preliminary
16 15
frame_thres_rx1_9
R/W-0
Descriptions
16 15
frame_thres_rx1_13
R/W-0
Descriptions
www.ti.com
Figure 20-52 and described in
8 7
frame_thres_rx1_8
R/W-0
Figure 20-54 and described in
8 7
frame_thres_rx1_12
R/W-0
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
0
0