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20.9.2.1.13 USB0 IRQ_ENABLE_CLR_1 Register (USB0IRQENABLECLR1)
The USB0 IRQ_ENABLE_CLR_1 register (USB0IRQENABLECLR1) allows the USB0 interrupt sources
to be manually disabled when writing a 1 to a specific bit. A read of this register returns the USB0
interrupt enabled value. General actions per bit:
Write 0: No action
Write 1: Disable interrupt
Read 0: Interrupt disabled
Read 1: Interrupt enabled
The USB0 IRQ_ENABLE_CLR_1 register is shown in
Figure 20-77. USB0 IRQ_ENABLE_SET_1 Register (USB0IRQENABLECLR1)
31
30
29
28
TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO
15
14
13
12
R/W-0h
R/W-0h
R/W-0h
R/W-0h
15
Reserved
R/0-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-88. USB0 IRQ_ENABLE_CLR_1 Register (USB0IRQENABLECLR1) Field Descriptions
Bits
Field
31
TX FIFO 15
30
TX FIFO 14
29
TX FIFO 13
28
TX FIFO 12
27
TX FIFO 11
26
TX FIFO 10
25
TX FIFO 9
24
TX FIFO 8
23
TX FIFO 7
22
TX FIFO 6
21
TX FIFO 5
20
TX FIFO 4
19
TX FIFO 3
18
TX FIFO 2
17
TX FIFO 1
16
TX FIFO 0
15-10
Reserved
9
USB[9]
8
USB[8]
7
USB[7]
6
USB[6]
5
USB[5]
4
USB[4]
3
USB[3]
2
USB[2]
1
USB[1]
0
USB[0]
SPRUGX9 – 15 April 2011
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Preliminary
27
26
25
24
11
10
9
8
R/W-0h
R/W-0h
R/W-0h
R/W-0h
10
9
8
USB[9]
USB[8]
R/W-0h
R/W-0h
Description
Interrupt enable for TX FIFO endpoint 15
Interrupt enable for TX FIFO endpoint 14
Interrupt enable for TX FIFO endpoint 13
Interrupt enable for TX FIFO endpoint 12
Interrupt enable for TX FIFO endpoint 11
Interrupt enable for TX FIFO endpoint 10
Interrupt enable for TX FIFO endpoint 9
Interrupt enable for TX FIFO endpoint 8
Interrupt enable for TX FIFO endpoint 7
Interrupt enable for TX FIFO endpoint 6
Interrupt enable for TX FIFO endpoint 5
Interrupt enable for TX FIFO endpoint 4
Interrupt enable for TX FIFO endpoint 3
Interrupt enable for TX FIFO endpoint 2
Interrupt enable for TX FIFO endpoint 1
Interrupt enable for TX FIFO endpoint 0
Always read 0. Writes have no effect.
Interrupt enable for Mentor controller USB_INT generic interrupt
Interrupt enable for DRVVBUS level change
Interrupt enable for VBUS < VBUS valid threshold
Interrupt enable for SRP detected
Interrupt enable for device disconnected (host mode)
Interrupt enable for device connected (host mode)
Interrupt enable for SOF started
Interrupt enable for Reset signaling detected (peripheral mode)
Babble detected (host mode)
Interrupt enable for Resume signaling detected
Interrupt enable for Suspend signaling detected
© 2011, Texas Instruments Incorporated
Figure 20-77
and described in
23
22
21
20
7
6
5
4
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
USB[7]
USB[6]
USB[5]
USB[4]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Registers
Table
20-88.
19
18
17
16
3
2
1
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
3
2
1
0
USB[3]
USB[2]
USB[1]
USB[0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
1873
Universal Serial Bus (USB)
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