Nand Read Cycle Optimization Timing Description - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
5.2.4.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
Access time to a NAND memory device can be optimized for back-to-back accesses if the associated
CS signal is not deasserted between accesses. The GPMC access engine can track prefetch engine
accesses to optimize the access timing parameter programmed for the allocated chip-select, if no
accesses to other chip-selects (that is, interleaved accesses) occur. Similarly, the access engine also
eliminates the CYCLE2CYCLEDELAY even if CYCLE2CYCLESAMECSEN is set. This capability is
limited to the prefetch and write-posting engine accesses, and MPU accesses to a NAND memory
device (through the defined chip-select memory region or through the GPMC_NAND_DATA_i(where , i
= 0 to 7) are never optimized.
The GPMC_PREFETCH_CONFIG1[27] ENABLEOPTIMIZEDACCESS bit must be set to enable
optimized accesses. To optimize access time, the GPMC_PREFETCH_CONFIG1[30-28]
CYCLEOPTIMIZATION field defines the number of GPMC_FCLK cycles to be suppressed from the
RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSOFFTIME, ADVOFFTIME,
OEOFFTIME, and WEOFFTIME timing parameters.
Figure 5-41, in the case of back-to-back accesses to the NAND flash through the prefetch engine,
CYCLE2CYCLESAMECSEN is forced to 0 when using optimized accesses. The first access uses the
regular timing settings for this chip-select. All accesses after this one use settings reduced by x clock
cycles, x being defined by the GPMC_PREFETCH_CONFIG1[30-28] CYCLEOPTIMIZATION field.
Figure 5-41. NAND Read Cycle Optimization Timing Description
GPMC_FCLK
nCS
nBE0/CLE
nOE/nRE
nADV/ALE
D[15:0]
WAIT
632
General-Purpose Memory Controller (GPMC)
Preliminary
RDACCESSTIME
First read access
RDCYCLETIME
CSRDOFFTIME
CSONTIME = 0
OEONTIME = 0
OEOFFTIME
Data 0
© 2011, Texas Instruments Incorporated
RDACCESSTIME - x clk cycles
Second read access
RDCYCLETIME − x clk cycles
CSRDOFFTIME − x clk cycles
CSONTIME = 0
OEONTIME = 0
OEOFFTIME − x clk cycles
Data 1
x is the programmed value in the
GPMC_PREFETCH_CONFIG1[30:28]
CYCLEOPTIMIZATION field
Submit Documentation Feedback
www.ti.com
SPRUGX9 – 15 April 2011