Architectural Highlights Of The 7 Series Fpga Dsp48E1 Slice - Xilinx 7 Series User Manual

Chapter 2: DSP48E1 Description and Specifics

Architectural Highlights of the 7 Series FPGA DSP48E1 Slice

The 7 series FPGA DSP48E1 slice is functionally equivalent to the Virtex-6 FPGA DSP48E1.
The 7 series FPGA DSP48E1 slice contains a pre-adder after the A register with a 25-bit
input vector called D. The D register can be used either as the pre-adder register or an
alternate input to the multiplier. The DSP48E1 specific features are highlighted in
Figure
X-Ref Target - Figure 2-2
B
18
BCIN
BCOUT* ACOUT*
18
B
Dual B Register
A
30
Dual A, D,
18
and Pre-adder
30
D 25
C
4
INMODE 5
CARRYIN
OPMODE
CARRYINSEL
BCIN* ACIN*
A
30
ACIN
D
25
Figure 2-2: Hierarchical View of the 7 Series DSP48E1 Slice Input Registers and Pre-adder
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2-2. More detailed descriptions are found starting at
B1
CEB2 RSTB
CEB1 RSTB
48
A:B
30
18
18
B
MULT
M
25 X 18
30
25
48
C
1
A2
A1
CEA1 RSTA
CEA2 RSTA
INMODE[0]
D
INMODE[2]
INMODE[3]
CED RSTD
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B2
INMODE[4]
ALUMODE
4
X
0
0
Y
1
0
17-Bit Shift
Z
17-Bit Shift
3
7
30
30
25
INMODE[1]
+
AD
–
25
CEAD RSTD
Input Ports, page 29.
BCOUT
18
X MUX
18
B MULT
18
CARRYCASCOUT*
MULTSIGNOUT* PCOUT*
P
48
P
CARRYOUT
48
P
PATTERNDETECT
P
PATTERNBDETECT
CREG/C Bypass/Mask
MULTSIGNIN*
CARRYCASCIN*
ACOUT
48
PCIN*
X MUX
A MULT
25
UG369_c1_02_072209
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
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