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12
12.3 Transmit Operation in CSIO Mode
12.3.1 Setting the CSIO Baud Rate
The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The
clock source from which to generate the transmit/receive shift clock is selected from the internal
clock f(BCLK) or external clock. The CKS (internal/external clock select) bit (SIO Transmit/Receive
Mode Register D11 bit) is used to select the clock source. The equation by which to calculate the
transmit/receive baud rate values differs with the selected clock source, whether internal or
external.
(1) When internal clock is selected in CSIO mode
When the internal clock is selected, f(BCLK) is divided by the clock divider before being fed into
the baud rate generator (BRG).
The clock divider's divide-by value is selected from 1, 8, 32, or 256 by using the CDIV (baud rate
generator count source select) bits (Transmit Control Register D2, D3 bits). The baud rate
generator divides the clock divider output by (baud rate register set value + 1) and then by 2,
which results in generating a transmit/receive shift clock.
When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation
below.
Baud rate = ————————————————
Clock divider's divide-by value × (baud rate register set value + 1) × 2
[bps]
Note : If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK)
itself), make sure the baud rate register value you set does not exceed 2 Mbps.
(2) When external clock is selected in CSIO mode
In this case, the baud rate generator is not used; instead, the input clock from the SCLKI pin
serves directly as CSIO transmit/receive shift clock.
The maximum frequency of the SCLKI pin input clock is 1/16 of f(BCLK).
1 (BCLK)
Baud rate register set value = H'00 to H'FF (Note)
Clock divider's divide-by value = 1, 8, 32, or 256
Baud rate = SCLKI pin input clock
[bps]
12-28
12.3 Transmit Operation in CSIO Mode
SERIAL I/O
Ver.0.10
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