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Appendix 2
Appendix 2.1 32170 Instruction Processing Time
For the M32R, the number of instruction execution cycles in E stage normally represents its
instruction processing time. However, depending on pipeline operation, other stages may affect the
instruction processing time. Especially when a branch instruction is executed, the processing time
in IF (instruction fetch) and D (decode) stages, not just E (execution) stage, must also be taken into
account.
The table below shows the instruction processing time in each pipelined stage of the M32R.
Table 2.1.1 Instruction Processing Time of Each Pipeline Stage
Instruction
Load instructions (LD, LDB, LDUB, LDH, LDUH, LOCK)
Store instructions (ST,STB,STH,UNLOCK)
Multiply instruction (MUL)
Divide/remainder instructions (DIV, DIVU,REM,REMU)
Other instructions (including those for DSP function)
Note: For R and W, refer to the calculation methods described in the next page.
INSTRUCTION PROCESSING TIME
Appendix 2.1 32170 Instruction Processing Time
Number of execution cycles in each stage (Note 1)
IF
R
R
R
R
R
Appendix 2-2
D
E
MEM
1
1
R
1
1
W
1
3
-
1
37
-
1
1
-
WB
1
-
1
1
1
Ver.0.10
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