10
10.6.3 TML Related Register Map
The diagram below shows a TML related register map.
Address
H'0080 03E0
H'0080 03E2
H'0080 03EA
H'0080 03F0
H'0080 03F2
H'0080 03F4
H'0080 03F6
H'0080 03F8
H'0080 03FA
H'0080 03FC
H'0080 03FE
H'0080 0FE0
H'0080 0FE2
H'0080 0FEA
H'0080 0FF0
H'0080 0FF2
H'0080 0FF4
H'0080 0FF6
H'0080 0FF8
H'0080 0FFA
H'0080 0FFC
H'0080 0FFE
Blank addresses are reserved.
Note: The registers enclosed in thick frames must always be accessed
Figure 10.6.2 TML Related Register Map
+0 Address
D0
TML0 Counter, High (TML0CTH)
TML0 Counter, Low (TML0CTL)
TML0 Measure 3 Register, High (TML0MR3H)
TML0 Measure 3 Register, Low (TML0MR3L)
TML0 Measure 2 Register, High (TML0MR2H)
TML0 Measure 2 Register, Low (TML0MR2L)
TML0 Measure 1 Register, High (TML0MR1H)
TML0 Measure 1 Register, Low (TML0MR1L)
TML0 Measure 0 Register, High (TML0MR0H)
TML0 Measure 0 Register, Low (TML0MR0L)
TML1 Counter, High (TML1CTH)
TML1 Counter, Low (TML1CTL)
TML1 Measure 3 Register, High (TML1MR3H)
TML1 Measure 3 Register, Low (TML1MR3L)
TML1 Measure 2 Register, High (TML1MR2H)
TML1 Measure 2 Register, Low (TML1MR2L)
TML1 Measure 1 Register, High (TML1MR1H)
TML1 Measure 1 Register, Low (TML1MR1L)
TML1 Measure 0 Register, High (TML1MR0H)
TML1 Measure 0 Register, Low (TML1MR0L)
in halfwords.
10-151
MULTIJUNCTION TIMERS
10.6 TML (Input-related 32-bit Timer)
+1 Address
D7 D8
TML0 Control Register
(TML0CR)
TML1 Control Register
(TML1CR)
D15
Ver.0.10