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12
(1) RSTAT (receive status) bit
[Set condition]
This bit is set to 1 by a start of receive operation. When this bit = 1, it means that the serial
I/O is receiving data.
[Clear condition]
This bit is cleared to 0 upon completion of receive operation or by clearing the REN
(receive enable) bit.
(2) RFIN (receive completed) bit
[Set condition]
This bit is set to 1 when all data bits have been received in the Receive Shift Register and
whose content is transferred to the Receive Buffer Register.
[Clear condition]
This bit is cleared to 0 by reading the lower byte from the Receive Buffer Register or by
clearing the REN (receive enable) bit. However, if an overrun error occurs, this bit cannot
be cleared by reading the lower byte from the Receive Buffer Register. In this case, clear
the REN (receive enable) bit.
(3) REN (receive enable) bit
Receive is enabled by setting this bit to 1, and is disabled by clearing this bit to 0, at which time
the receive unit is initialized. Accordingly, the receive status flag, receive-completed flag bit,
overrun error flag, framing error flag, parity error flag, and error sum flag all are cleared. The
receive operation stops when the receive enable bit is cleared to 0 while receiving data.
(4) OVR (overrun error) bit
[Set condition]
This bit is set to 1 when all bits of the next receive data have been received in the Receive
Shift Register while the Receive Buffer Register still contains the previous receive data. In
this case, the receive data is not stored in the Receive Buffer Register. Although receive
operation is continued when the overrun error flag = 1, the receive data is not stored in the
Receive Buffer Register. To start reception normally, you need to clear this bit.
[Clear condition]
This bit is cleared to 0 by only clearing the REN (receive enable) bit.
(D1)
(D2)
(D3)
(D4)
12-24
12.2 Serial I/O Related Registers
SERIAL I/O
Ver.0.10
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