Starting Dma; Channel Priority; Gaining And Releasing Control Of The Internal Bus - Mitsubishi Electric M32R Series User Manual

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9.3.3 Starting DMA

Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable
DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause
of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1.

9.3.4 Channel Priority

Channel 0 has the highest priority. The priority of this and other channels is shown below.
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 >
channel 8 > channel 9
This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are
requested, the channel that has the highest priority is selected. Channel selection is made every
transfer cycle (one DMA bus cycle consisting of three machine cycles).

9.3.5 Gaining and Releasing Control of the Internal Bus

For any channel, control of the internal bus is gained and released in "single transfer DMA" mode.
In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is
accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of
internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA
operation in single transfer DMA.
Requested
Internal bus
arbitration (control
requested by DMAC)
CPU
Internal
bus
DMAC
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
Gained Requested
Released
R W
One DMA transfer
9-32
9.3 Functional Description of the DMAC
Gained Requested
Released
R W
One DMA transfer
R: Read
W: Write
DMAC
Gained
Released
R W
One DMA transfer
Ver.0.10