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5
D0
(
D8
D
Bit Name
0 – 2
No functions assigned
(8-10)
3
IREQ (Interrupt request)
(11)
4
No functions assigned
(12)
5-7
ILEVEL (Interrupt priority level) 000 : Interrupt priority level 0
(13-15)
W=
: Can be set and cleared only when the type of input source is "Edge-recognized" type (with
only one interrupt source being input).
(1) IREQ (Interrupt Request) bit (D3 or D11)
When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ
(Interrupt Request) bit is set to 1.
This bit can be set and cleared in software for only edge-recognized interrupt sources (and not for
level-recognized interrupt sources). Also, when the IREQ bit is set by an interrupt request
generated by an edge-recognized interrupt source, it is automatically cleared to 0 by reading out
the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt
sources).
If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated,
clearing in software has priority. Also, if the IREQ bit is cleared by reading out the IVECT register
at the same time it is set by an interrupt request generated, clearing by a read of IVECT has
priority.
1
2
3
9
10
11
IREQ
Function
0 : Interrupt is not requested
1 : Interrupt is requested
001 : Interrupt priority level 1
010 : Interrupt priority level 2
011 : Interrupt priority level 3
100 : Interrupt priority level 4
101 : Interrupt priority level 5
110 : Interrupt priority level 6
111 : Interrupt priority level 7 (Interrupt-disabled state)
5-11
INTERRUPT CONTROLLER (ICU)
5.3 ICU-Related Registers
4
5
6
12
13
14
ILEVEL
D7
D15)
<When reset: H''07>
R
W
0
–
0
–
Ver.0.10
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