Mitsubishi Electric M32R Series User Manual page 604

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

Transmit enable bit

Transmit buffer

Transmit status bit

SIO transmit interrupt

Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit

Note 2 : When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the

same timing)

Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register"

interrupt request bit cleared

Note 4 : Transmit interrupt request is generated when transmission is enabled.

Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated

when the data is transferred from the transmit buffer to the transmit shift register and the transmit

buffer is thereby emptied.

Figure 12.6.6 Example of UART Transmission (Successive Transmission, with Transmit

Interrupt Used)

(First data)

Interrupt request accepted (Note 3)

: Processing by software

12.6 Transmit Operation in UART Mode

Transferred from

transmit buffer to

transmit shift register

(transmission starts)

Upon transmit interrupt,

next data is written

: Interrupt generation

Cleared when transmission

of last data is completed