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10
10.8.3 TOD Related Register Map
The diagram below shows a TOD related register map.
Address
H'0080 0790
H'0080 0792
H'0080 0794
H'0080 0796
H'0080 0798
H'0080 079A
H'0080 079C
H'0080 079E
H'0080 07A0
H'0080 07A2
H'0080 07A4
H'0080 07A6
H'0080 07A8
H'0080 07AA
H'0080 07AC
H'0080 07AE
H'0080 07B0
H'0080 07B2
H'0080 07B4
H'0080 07B6
H'0080 07B8
H'0080 07BA
H'0080 07BC
H'0080 07BE
Blank addresses are reserved.
Note : The registers enclosed in thick frames must always be accessed in halfwords.
Figure 10.8.2 TOD Related Register Map (1/3)
+0 Address
D0
TOD0_0 Counter (TOD00CT)
TOD0_0 Reload 1 Register (TOD00RL1)
TOD0_0 Reload 0 Register (TOD00RL0)
TID0_1 Counter (TOD01CT)
TOD0_1 Reload 1 Register (TOD01RL1)
TOD0_1 Reload 0 Register (TOD01RL0)
TID0_2 Counter (TOD02CT)
TOD0_2 Reload 1 Register (TOD02RL1)
TOD0_2 Reload 0 Register (TOD02RL0)
TID0_3 Counter (TOD03CT)
TOD0_3 Reload 1 Register (TOD03RL1)
TOD0_3 Reload 0 Register (TOD03RL0)
TID0_4 Counter (TOD04CT)
TOD0_4 Reload 1 Register (TOD04RL1)
TOD0_4 Reload 0 Register (TOD04RL0)
TID0_5 Counter (TOD05CT)
TOD0_5 Reload 1 Register (TOD05RL1)
TOD0_5 Reload 0 Register (TOD05RL0)
10-177
MULTIJUNCTION TIMERS
10.8 TOD (Output-related 16-bit Timer)
+1 Address
D7
D8
D15
Ver.0.10
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