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10
TIN Interrupt Control Register 7 (TINIR7)
D8
TINIS33
D
Bit Name
8
TINIS33 (TIN33 interrupt status)
9
TINIS32 (TIN32 interrupt status)
10
TINIS31 (TIN31 interrupt status)
11
TINIS30 (TIN30 interrupt status)
12
TINIM33 (TIN33 interrupt mask)
13
TINIM32 (TIN32 interrupt mask)
14
TINIM31 (TIN31 interrupt mask)
15
TINIM30 (TIN30 interrupt mask)
W =
: Only writing a 0 is effective; when you write a 1, the previous value is retained.
Note : For TIN24-TIN29, there are no interrupt status and mask bits in MJT interrupt control registers because
they do not have interrupt functions.
Data bus
Figure 10.2.19 Block Diagram of TML1 Input Interrupt
9
10
11
TINIS32
TINIS31
TINIS30
Function
0 : No interrupt request
1 : Interrupt request generated
0 : Enables interrupt request
1 : Masks (disables) interrupt request
TINIR7 <H'0080 023F>
TIN33edge
TINIS33
b8
F/F
TINIM33
b12
F/F
TIN32edge
TINIS32
b9
F/F
TINIM32
b13
F/F
TIN31edge
TINIS31
b10
F/F
TINIM31
b14
F/F
TIN30edge
TINIS30
b11
F/F
TINIM30
b15
F/F
10-56
<Address: H'0080 023F>
12
13
TINIM33
TINIM32
TINIM31
4-source inputs
(Level)
14
D15
TINIM30
<When reset : H'00>
R
W
TML1 input
interrupt
IRQ18
Ver.0.10
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