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5
5.3.1 Interrupt Vector Register
Interrupt Vector Register (IVECT)
D0
1
2
D
Bit Name
0 – 15
IVECT (16 low-order
bits of ICU vector
table address)
Note: This register must always be accessed in halfwords.
The Interrupt Vector Register (IVECT) is used when an interrupt is accepted to store the 16 low-
order bits of ICU vector table address for the accepted interrupt source.
Before this function can work, the ICU vector table (addresses H'0000 0094 through H'0000
010F) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O.
When an interrupt is accepted, the 16 low-order bits of ICU vector table address for the accepted
interrupt source is stored in this IVECT register. The EIT handler reads out the content of the
IVECT register by the "LDH" instruction to acquire the ICU vector table address.
When the IVECT register is read out, operations (1) to (4) below are automatically performed in
hardware:
(1) The accepted new IMASK (NEW_IMASK) is set in the IMASK register.
(2) The accepted interrupt request is cleared (not cleared for level-recognized interrupt
sources).
(3) The interrupt request (EI) to the CPU core is cleared.
(4) The ICU's internal sequencer is activated to start internal processing (interrupt priority
resolution).
Note that the Interrupt Vector Register (IVECT) can only be read out by the EIT handler (PSW
register IE bit being disabled). Also, make sure that in the EIT handler, the Interrupt Mask
Register (IMASK) is read out before reading out the IVECT register.
3
4
5
6
Function
When an interrupt is accepted, the 16 low-order bits
in ICU vector table address for the accepted
interrupt source is stored in this register.
CAUTION
5-7
INTERRUPT CONTROLLER (ICU)
7
8
9
10
11
IVECT
5.3 ICU-Related Registers
<Address:H'0080 0000>
12
13
14
D15
<When reset: Indeterminate>
R
W
–
Ver.0.10
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