Dma Transfer Processing Procedure - Mitsubishi Electric M32R Series User Manual

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9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer in
DMA channel 0.
Setting interrupt
controller related
registers
Setting DMAC
related registers
Starting DMA
transfer
DMA transfer
completed
Figure 9.3.1 Example of a DMA Transfer Processing Procedure
DMA transfer processing starts
Set the interrupt controller's DMA0-4
Interrupt Control Register
Set DMA0 Channel Control Register
Set DMA0-4 Interrupt Request Status Register
Set DMA0-4 Interrupt Mask Register
Set DMA0 Source Address Register
Set DMA0 Destination Address Register
Set DMA0 Count Register
Set DMA0 Channel Control Register
DMA transfer starts as requested by
internal peripheral I/O
Transfer count register underflows
Interrupt request generated
DMA operation completed
9-31
9.3 Functional Description of the DMAC
• Interrupt priority level
• Transfers disabled
• Clears interrupt request
status bit
• Enables interrupt request
• Source address of transfer
• Address
• Number of times DMA
transfer performed
• Transfer mode, cause of
request, transfer size,
address direction, and
transfer enable
DMAC
Ver.0.10