Mitsubishi Electric M32R Series User Manual page 73

Mitsubishi 32-bit risc single-chip microcomputers
Table of Contents

Advertisement

3
Address
D0
H'0080 03BC
H'0080 03BE
H'0080 03C0
H'0080 03C2
H'0080 03C4
H'0080 03C6
H'0080 03C8
H'0080 03CA
~ ~
H'0080 03D0
H'0080 03D2
H'0080 03D4
H'0080 03D6
H'0080 03D8
~ ~
H'0080 03E0
H'0080 03E2
~ ~
H'0080 03EA
~ ~
H'0080 03F0
H'0080 03F2
H'0080 03F4
H'0080 03F6
H'0080 03F8
H'0080 03FA
H'0080 03FC
H'0080 03FE
H'0080 0400
~ ~
H'0080 0408
~ ~
H'0080 0410
H'0080 0412
H'0080 0414
H'0080 0416
H'0080 0418
H'0080 041A
H'0080 041C
H'0080 041E
H'0080 0420
H'0080 0422
H'0080 0424
H'0080 0426
H'0080 0428
H'0080 042A
H'0080 042C
H'0080 042E
Blank addresses are reserved areas.
Figure 3.4.9 Register Mapping of the SFR Area (6)
+0 Address
TMS0 Control Register (TMS0CR)
TML0 Measure 3 Register, High (TML0MR3H)
TML0 Measure 3 Register, Low (TML0MR3L)
TML0 Measure 2 Register, High (TML0MR2H)
TML0 Measure 2 Register, Low (TML0MR2L)
TML0 Measure 1 Register, High (TML0MR1H)
TML0 Measure 1 Register, Low (TML0MR1L)
TML0 Measure 0 Register, High (TML0MR0H)
TML0 Measure 0 Register, Low (TML0MR0L)
DMA0-4 Interrupt Request Status Register (DM04ITST)
DMA5-9 Interrupt Request Status Register (DM59ITST)
DMA0 Channel Control Register (DM0CNT)
DMA0 Destination Address Register (DM0DA)
DMA5 Channel Control Register (DM5CNT)
DMA5 Destination Address Register (DM5DA)
DMA1 Channel Control Register (DM1CNT)
DMA1 Destination Address Register (DM1DA)
DMA6 Channel Control Register (DM6CNT)
DMA6 Destination Address Register (DM6DA)
D7 D8
TIO0-9 Enable Protect Register (TIOPRO)
TIO0-9 Count Enable Register (TIOCEN)
TMS0 Counter (TMS0CT)
TMS0 Measure 3 Register (TMS0MR3)
TMS0 Measure 2 Register (TMS0MR2)
TMS0 Measure 1 Register (TMS0MR1)
TMS0 Measure 0 Register (TMS0MR0)
TMS1 Control Register (TMS1CR)
TMS1 Counter (TMS1CT)
TMS1 Measure 3 Register (TMS1MR3)
TMS1 Measure 2 Register (TMS1MR2)
TMS1 Measure 1 Register (TMS1MR1)
TMS1 Measure 0 Register (TMS1MR0)
TML0 Counter, High (TML0CTH)
TML0 Counter, Low (TML0CTL)
TML0 Control Register (TML0CR)
DMA0-4 Interrupt Mask Register (DM04ITMK)
DMA5-9 Interrupt Mask Register (DM59ITMK)
DMA0 Transfer Count Register (DM0TCT)
DMA0 Source Address Register (DM0SA)
DMA5 Transfer Count Register (DM5TCT)
DMA5 Source Address Register (DM5SA)
DMA1 Transfer Count Register (DM1TCT)
DMA1 Source Address Register (DM1SA)
DMA6 Transfer Count Register (DM6TCT)
DMA6 Source Address Register (DM6SA)
3-17
ADDRESS SPACE
3.4 Internal ROM/SFR Area
+1 Address
D15
Ver.0.10
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~

Advertisement

Table of Contents
loading

Table of Contents