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2
2.3.1 Processor Status Word Register: PSW (CR0)
The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists
of a regularly used PSW field and a special BPSW field which is used to save the PSW field when
an EIT occurs.
The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and
Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit
(BSM), Backup IE bit (BIE), and Backup C bit (BC).
0(MSB)
PSW
0
0
0
0
D
Bit Name
16
BSM (Backup SM)
17
BIE (Backup IE)
23
BC (Backup C)
24
SM (Stack Mode)
25
IE (Interrupt Enable)
31
C (Condition bit)
Notes 1: "Initial" shows the state immediately after reset, R = O means the register is readable, W = O
means the register is writable.
2: For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT."
7
8
0
0
0
0
0
0
0
0
0
Function
Holds the value of SM bit when EIT
is accepted.
Holds the value of IE bit when EIT
is accepted.
Holds the value of C bit when EIT
is accepted.
0: Interrupt stack pointer is used.
1: User stack pointer is used.
0: No interrupt is accepted.
1: Interrupt is accepted.
Depending on instruction execution, it indicates
whether operation resulted in a carry, borrow, or overflow.
2-4
BPSW field
15
16 17
0
0
0
0
0
0
0
BSM
BIE
BC
2.3 Control Registers
PSW field
31(LSB)
23 24 25
0
0
0
0
0
0
SM
IE
(Note 1)
Initial
R
W
Indeterminate
Indeterminate
Indeterminate
0
0
0
Ver.0.10
CPU
C
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