Address Exception (Ae) - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

4.8.2 Address Exception (AE)

[Occurrence Conditions]

Address Exception (AE) is generated when an attempt is made to access a misaligned address

in Load or Store instructions. The following lists the combination of instructions and accessed

addresses that may cause address exceptions to occur:

• When the LDH, LDUH, or STH instruction accesssed an address whose two low-order bits are

"01" or "11"

• When the LD, ST, LOCK, or UNLOCK instruction accessed an address whose two low-order

bits are "01," "10," or "11"

When an address exception occurs, memory access by the instruction that generated the

exception is not performed. If an external interrupt is requested at the same time an address

exception is detected, it is the address exception that is accepted.

[EIT Processing]

(1) Saving SM, IE, and C bits

The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE,

and BC bits.

(2) Updating SM, IE, and C bits

The SM, IE, and C bits of the PSW register are updated as shown below.

(3) Saving PC

The PC value of the instruction that generated the address exception is set in the BPC

4, the value 4 is set in the BPC register. Similarly, if the instruction is at address 6, the value

6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates

whether the instruction that generated the address exception resides on a word boundary

(BPC[30] = 0) or not on a word boundary (BPC[30] = 1).

However, in either case of the above, the address to which the "RTE" instruction returns

after completion of processing by the EIT handler is address 4. (This is because the two

low-order bits are cleared to "00" when returning to the PC.)

4.8 Exception Processing