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21
PRELIMINARY
PRELIMINARY
(4) Read and write timing
Symbol
t
BCLK Output Cycle Time
c(BCLK)
BCLK Output High Pulse Width
t
w(BCLKH)
t
BCLK Output Low Pulse Width
w(BCLKL)
Address Delay Time after BCLK
t
d(BCLKH-A)
Chip Select Delay Time after BCLK
t
d(BCLKH-CS)
Valid Address Time after BCLK
t
v(BCLKH-A)
Valid Chip Select Time after BCLK
t
v(BCLKH-CS)
Read Delay Time after BCLK
t
d(BCLKL-RDL)
Valid Read Time after BCLK
t
v(BCLKH-RDL)
t
d(BCLKL-BLWL)
Write Delay Time after BCLK
t
d(BCLKL-BHWL)
t
v(BCLKL-BLWL)
Valid Write Time after BCLK
t
d(BCLKL-D)
t
Data Output Delay Time after BCLK
v(BCLKL-BHWL)
t
v(BCLKH-D)
Valid Data Output Time after BCLK
t
pzx(BCLKL-DZ)
Data Output Enable Time after BCLK
t
pxz(BCLKH-DZ)
Data Output Disable Time after BCLK
t
Address Delay Time before Read
d(A-RDL)
t
d(CS-RDL)
Chip Select Delay Time before Read
t
v(RDH-A)
Valid Address Time after Read
t
Valid Chip Select Time after Read
v(RDH-CS)
Data Output Enable Time after Read
t
pzx(RDH-DZ)
t
d(A-BLWL)
Address Delay Time before Write
t
d(A-BHWL)
(Byte write mode)
t
d(CS-BLWL)
Chip Select Delay Time before Write
t
d(CS-BHWL)
(Byte write mode)
t
Valid Address Time after Write
v(BLWH-A)
t
(Byte write mode)
v(BHWH-A)
t
Valid Chip Select Time after Write
v(BLWH-CS)
t
(Byte write mode)
v(BHWH-CS)
Parameter
Condition
21-16
ELECTRICAL CHARACTERISTICS
21.5 AC Characteristics
Rated Value
MIN
tc(Xin)
tc(BCLK)
- 5
2
tc(BCLK)
- 5
2
-11
-11
-12
-12
-16
-19
tc(BCLK)
-15
2
tc(BCLK)
-15
2
0
0
tc(BCLK)
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
See
Figure
Unit
21.5.6
21.5.7
MAX
21.5.8
ns
16
2
ns
17
ns
18
24
ns
19
24
ns
20
ns
21
ns
22
10
ns
23
ns
24
11
ns
25
ns
26
18
27
ns
28
ns
29
ns
5
ns
30
ns
39
ns
40
ns
41
ns
42
ns
46
ns
47
ns
48
ns
49
ns
50
Ver.0.10
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