Page 1 ADVANCED AND EVER ADVANCING Preliminary -M32170-U-0003 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/E Series 32170 Group M32170F6VFP/WG M32170F4VFP/WG M32170F3VFP/WG User’s Manual 2000-03-17 Ver0.10 NOTE Information in this manual may be changed without prior notice. Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation...
Page 2 All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore...
Page 3 PREFACE This manual describes the hardware specifica- tions of Mitsubishi’s 32170 group of 32-bit CMOS microcomputers. This manual was created to help you under- stand the hardware specifications of the 32170-group microcomputers so you can take full advantage of the versatile performance ca- pabilities of these microcomputers.
Page 4 How to read internal I/O register tables Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column...
Page 5: Table Of Contents
Contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32170 ..................1-2 1.1.1 M32R Family CPU Core ................1-2 1.1.2 Built-in Multiply-Accumulate Operation Function ........1-3 1.1.3 Built-in Flash Memory and RAM ..............1-3 1.1.4 Built-in Clock Frequency Multiplier ............. 1-4 1.1.5 Built-in Powerful Peripheral Functions ............
Page 6 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space ................3-2 3.2 Operation Modes ....................3-6 3.3 Internal ROM Area and Extended External Area ..........3-8 3.3.1 Internal ROM Area ..................3-8 3.3.2 Extended External Area ................3-8 3.4 Internal RAM Area and SFR Area ..............3-9 3.4.1 Internal RAM Area ..................
Page 7 4.9.3 External Interrupt (EI) ................4-18 4.10 Trap Processing .................... 4-20 4.10.1 Trap (TRAP) ................... 4-20 4.11 EIT Priority Levels ..................4-22 4.12 Example of EIT Processing ................4-23 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of Interrupt Controller (ICU) ..............5-2 5.2 Interrupt Sources of Internal Peripheral I/Os ..........
Page 8 6.4.4 Virtual Flash L Bank Registers ..............6-14 6.4.5 Virtual Flash S Bank Registers ..............6-15 6.5 Programming of the Internal Flash Memory ..........6-16 6.5.1 Outline of Programming Flash Memory ............ 6-16 6.5.2 Controlling Operation Mode during Programming Flash ......6-22 6.5.3 Programming Procedure to the Internal Flash Memory ......
Page 9 8.4 Port Peripheral Circuits .................. 8-31 CHAPTER 9 DMAC 9.1 Outline of the DMAC ..................9-2 9.2 DMAC Related Registers .................. 9-4 9.2.1 DMA Channel Control Register ..............9-6 9.2.2 DMA Software Request Generation Registers ......... 9-17 9.2.3 DMA Source Address Registers ............... 9-18 9.2.4 DMA Destination Address Registers ............
Page 10 10.2.4 Input Processing Control Unit ............... 10-18 10.2.5 Output Flip-Flop Control Unit ..............10-26 10.2.6 Interrupt Control Unit ................10-37 10.3 TOP (Output-related 16-bit Timer) ............. 10-63 10.3.1 Outline of TOP ..................10-63 10.3.2 Outline of Each Mode of TOP ............... 10-65 10.3.3 TOP Related Register Map ..............
Page 11 10.5.3 TMS Related Register Map ..............10-142 10.5.4 TMS Control Registers ............... 10-143 10.5.5 TMS Counters (TMS0CT, TMS1CT) ..........10-145 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) ....... 10-146 10.5.7 Operation of TMS Measure Input ............10-147 10.6 TML (Input-related 32-bit Timer) .............. 10-149 10.6.1 Outline of TML ..................
Page 12 10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function) . 10-201 10.9 TOM (Output-related 16-bit Timer) ............10-203 10.9.1 Outline of TOM ................... 10-203 10.9.2 Outline of Each Mode of TOM ............10-205 10.9.3 TOM Related Register Map ..............10-207 10.9.4 TOM Control Registers ...............
Page 13 11.3 Functional Description of A-D Converters ..........11-41 11.3.1 How to Find Along Input Voltages ............11-41 11.3.2 A-D Conversion by Successive Approximation Method ....... 11-42 11.3.3 Comparator Operation ................11-44 11.3.4 Calculation of the A-D Conversion Time ..........11-45 11.3.5 Definition of the A-D Conversion Accuracy ...........
Page 14 12.4.4 About Successive Reception ..............12-39 12.4.5 Flags Indicating the Status of CSIO Receive Operation ....... 12-40 12.4.6 Typical CSIO Receive Operation ............12-41 12.5 Precautions on Using CSIO Mode ............. 12-43 12.6 Transmit Operation in UART Mode ............12-45 12.6.1 Setting the UART Baud Rate ..............
Page 15 13.2.8 CAN Interrupt Related Registers ............13-22 13.2.9 CAN Mask Registers ................13-30 13.2.10 CAN Message Slot Control Registers ..........13-34 13.2.11 CAN Message Slots ................13-38 13.3 CAN Protocol ....................13-53 13.3.1 CAN Protocol Frame ................13-53 13.4 Initializing the CAN Module ................ 13-56 13.4.1 Initialization of the CAN Module ............
Page 16 14.3.5 Operation of VEI (Interrupt Request) ............ 14-10 14.3.6 Operation of RCV (Recover from Runaway) ........14-11 14.3.7 Method to Set a Specified Address when Using the RTD ....14-12 14.3.8 Resetting the RTD ................14-13 14.4 Typical Connection with the Host ............. 14-14 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals ............
Page 17 CHAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit ................... 18-2 18.1.1 Example of an Oscillator Circuit .............. 18-2 18.1.2 System Clock Output Function ............... 18-3 18.1.3 Oscillation Stabilization Time at Power-on ..........18-4 18.2 Clock Generator Circuit ................18-5 CHAPTER 19 JTAG 19.1 Outline of JTAG .....................
Page 18 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ................. 21-2 21.2 Recommended Operating Conditions ............21-3 21.3 DC Characteristics ..................21-5 21.3.1 Electrical Characteristics ................ 21-5 21.3.2 Flash Related Electrical Characteristics ..........21-10 21.4 A-D Conversion Characteristics ..............21-11 21.5 AC Characteristics ..................21-12 21.5.1 Timing Requirements ................
Page 19: Chapter 1 Overview
CHAPTER 1 CHAPTER 1 OVERVIEW 1.1 Outline of the 32170 1.2 Block Diagram 1.3 Pin Function 1.4 Pin Layout...
Page 20: M32R Family Cpu Core
OVERVIEW 1.1 Outline of the 32170 1.1 Outline of the 32170 1.1.1 M32R Family CPU Core (1) Based on RISC architecture • The 32170 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core (hereafter referred to as the M32R) and incorporates flash memory, RAM, and various other peripheral functions-all integrated into a single chip.
Page 21: Built-In Multiply-Accumulate Operation Function
OVERVIEW 1.1 Outline of the 32170 1.1.2 Built-in Multiply-Accumulate Operation Function (1) Built-in high-speed multiplier • The M32R incorporates a 32-bit × 16-bit high-speed multiplier which enables it to execute a 32-bit × 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 MHz internal CPU clock).
Page 22: Built-In Clock Frequency Multiplier
OVERVIEW 1.1 Outline of the 32170 1.1.4 Built-in Clock Frequency Multiplier • The 32170 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2. If the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 MHz and the internal clock frequency 20 MHz.
Page 23 OVERVIEW 1.1 Outline of the 32170 (4) High-speed serial I/O • The 32170 incorporates 6 channels of serial I/O, which can be set for clock-synchronized serial I/O or UART. • When set for clock-synchronized serial I/O, the data transfer rate is a high 2 Mbits per second. •...
Page 24: Built-In Full-Can Function
OVERVIEW 1.1 Outline of the 32170 1.1.6 Built-in Full-CAN Function • The 32170 contains CAN Specification V2.0B-compliant CAN module, thereby providing 16 message slots. 1.1.7 Built-in Debug Function • The 32170 supports JTAG interface. Boundary scan test can be performed using this JTAG interface.
Page 25: Block Diagram
OVERVIEW 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32170. Features of each block are shown in Tables 1.2.1 through 1.2.3. 32170 Internal bus interface M32R CPU core (max 40MHz) DMAC Multiplier- (10 channels) accumulator (32 X 16 + 56) Multijunction timer...
Page 26 OVERVIEW 1.2 Block Diagram Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock) Logical address space: 4Gbytes, linear Extended external area: Maximum 4 Mbytes External data bus: 16 bits •...
Page 27 OVERVIEW 1.2 Block Diagram Table 1.2.3 Features of Internal Peripheral I/O Functional Block Features • 10-channel DMA • Supports transfer between internal peripheral I/Os and between internal peripheral I/O and internal RAM. • Capable of advanced DMA transfer when operating in combination with internal peripheral I/O •...
Page 28: Pin Function
OVERVIEW 1.3 Pin Function 1.3 Pin Function Figure 1.3.1 shows a pin function diagram of the 32170 in 240QFP package. Figure 1.3.2 shows a pin function diagram of the 32170 in 255FBGA package. Table 1.3.1 explains the function of each pin of the 32170. Table 1.3.2 explains the function of the dedicated debug pins of the 32170 in 255FBGA package.
Page 29 OVERVIEW 1.3 Pin Function P45/CS1 XOUT P44/CS0 Clock VCNT P43/RD Port 4 OSC-VCC P42/BHW/BHE OSC-VSS control P41/BLW/BLE Port 7 P70/BCLK/WR P71/WAIT P72/HREQ Port 7 Reset RESET P73/HACK MOD0 Mode MOD1 P224/A11 (Note2) P225/A12 (Note2) Port 22 P220/CTX Port 2 Address Port 22 Port 3 P221/CRX...
Page 30 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (1/6) Type Pin Name Signal Name Input/Output Function Power VCCE Power supply — Power supply to external I/O ports (5 V). supply VCCI Power supply — Power supply to internal logic (3.3 V). RAM power supply —...
Page 31 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (2/6) Type Pin Name Signal Name Input/Output Function Data DB0-DB15 Data bus Input/Output These pins comprise 16-bit data bus to connect external devices. In write cycles, the valid byte positions to be written on the 16-bit data bus are output as BHW/BHE and BLW/BLE.
Page 32 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (3/6) Type Pin Name Signal Name Input/Output Function VREF0, Reference Input VREF0 is the reference voltage input pin for the A-D0 converter. converter VREF1 voltage input VREF1 is the reference voltage input pin for the A-D1 converter. _____ ADTRG Conversion...
Page 33 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (4/6) Type Pin Name Signal Name Input/Output Function TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1. RXD1 Receive data Input Receive data input pin for serial I/O channel 1. TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2.
Page 34 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (5/6) Type Pin Name Signal Name Input/Output Function Input/ P00 – P07 Input/output Input/output Programmable input/output port. output port 0 port P10 – P17 Input/output Input/output Programmable input/output port. (Note) port 1 P20 –...
Page 35 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (6/6) Type Pin Name Signal Name Input/Output Function Input/ P172 Input/output Input/output Programmable input/output port. output – P177 port 17 port P180 Input/output Input/output Programmable input/output port. – P187 port 18 P190 Input/output...
Page 36: Pin Layout
OVERVIEW 1.4 Pin Layout 1.4 Pin Layout Figure 1.4.1 shows a pin layout diagram of the 32170 in 240QFP package. Figure 1.4.2 shows a pin layout diagram of the 32170 in 255FBGA package. Table 1.4.1 lists pin assignments of the 240QFP.
Page 37 OVERVIEW 1.4 Pin Layout Table 1.4.1 Pin Assignments of the 240QFP (1/2) Pin Name Pin Name Pin Name Pin Name AD1IN12 P26 / A29 P87 / SCLKI1 / SCLKO1 AD1IN13 P27 / A30 P180 / TO29 P200 / TXD4 AD1IN14 P00 / DB0 P181 / TO30 P201 / RXD4...
Page 38 OVERVIEW 1.4 Pin Layout Table 1.4.1 Pin Assignments of the 240QFP (2/2) Pin Name Pin Name Pin Name Pin Name P112 / TO2 JTMS P134 / TIN20 P156 / TIN6 P113 / TO3 JTCK P135 / TIN21 P157 / TIN7 P114 / TO4 JTRST P136 / TIN22...
Page 39 OVERVIEW 1.4 Pin Layout P216 P214 P210 P102 P116 TRDATA P112 P77/ P202 P201 TRDATA JTMS VCCE RESET VCCE /TO43 /TO41 /TO37 /TO10 /TO6 /TO2 /TO19 RTDCLK /HACK /SCLK5 /TXD5 /RXD4 P217 P215 P211 P117 TRDATA P113 P76/ P200 TRDATA JTCK MOD0 VCCI...
Page 40 OVERVIEW 1.4 Pin Layout Table 1.4.2 Pin Assignments of the 255FBGA (1/2) Pin Name Pin Name Pin Name Pin Name — AD1IN14 P220 / CTX VCNT ______ AD1IN9 AD1IN13 P47 / A14 _____ AD1IN8 AD1IN4 P46 / A13 OSC-VOC _____ AD1IN6 AD1IN5 P45 / CS1...
Page 41 OVERVIEW 1.4 Pin Layout Table 1.4.2 Pin Assignments of the 255FBGA (2/2) Pin Name Pin Name Pin Name Pin Name P36 / A21 P00 / DB0 P12 / DB10 P16 / DB14 P37 / A22 P01 / DB1 P13 / DB11 VREF0 P20 / A23 P02 / DB2...
Page 42 OVERVIEW 1.4 Pin Layout This is a blank page. 1-24 Ver.0.10...
Page 43: Cpu Registers
CHAPTER 2 CHAPTER 2 2.1 CPU Registers 2.2 General-purpose Registers 2.3 Control Registers 2.4 Accumulator 2.5 Program Counter 2.6 Data Formats...
Page 44 2.1 CPU Registers 2.1 CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses.
Page 45: Control Registers
2.3 Control Registers 2.3 Control Registers There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. Control Registers Processor status Word Register Condition Bit Register...
Page 46: Processor Status Word Register: Psw (Cr0)
2.3 Control Registers 2.3.1 Processor Status Word Register: PSW (CR0) The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs.
Page 47: Condition Bit Register: Cbr (Cr1)
2.3 Control Registers 2.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC"...
Page 48: Accumulator
2.4 Accumulator 2.4 Accumulator The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0--7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed.
Page 49: Data Formats
2.6 Data Formats 2.6 Data Formats 2.6.1 Data Types There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements.
Page 50: Data Formats
2.6 Data Formats 2.6.2 Data Formats (1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register.
Page 51 2.6 Data Formats (2) Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00").
Page 52 2.6 Data Formats (3) Endian The following shows the generally used endian methods and the M32R family endian. Bit endian Byte endian (H'01) (H'01234567) B'0000001 Big endian H'01 H'23 H'45 H'67 Little endian B'0000001 H'45 H'23 H'01 H'67 Note: Even for bit big endian, H'01 is not B'10000000. Figure 2.6.4 Endian Methods M32R family 7700 family...
Page 53 2.6 Data Formats (4) Transfer instructions • Constant transfer LD24 Rdest, #imm24 imm24 LD24 Rdest, #imm24 Rdest, #imm16 Rdest Rdest, #imm8 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 Rdest • Register to register transfer Rdest, Rsrc Rdest, Rsrc Rsrc Rdest •...
Page 54 2.6 Data Formats (5) Memory (signed) to register transfer Memory Register • Signed 32 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc • Signed 16 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc Check the MSB 0 = positive 1 = negative •...
Page 55 2.6 Data Formats (7) Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Data in memory Data in register (R0-R15) Word data (32 bits) (R0-R15) Half-word data (16 bits) (R0-R15) Byte data (8 bits) MSB LSB...
Page 56 This is a blank page. 2-14 Ver.0.10...
Page 57: Chapter 3 Address Space
CHAPTER 3 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space 3.2 Operation Modes 3.3 Internal ROM Area and Extended External Area 3.4 Internal RAM Area and SFR Area 3.5 EIT Vector Entry 3.6 ICU Vector Table 3.7 Note about Address Space...
Page 58: Internal Rom Area
ADDRESS SPACE 3.1 Outline of Address Space 3.1 Outline of Address Space The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear ad- dress space. The M32R/E's address space consists of the following: (1) User space •...
Page 59 ADDRESS SPACE 3.1 Outline of Address Space Extended external <Logical address space of M32170F6> area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (768 Kbytes) (16 Mbytes) (Note 1) H'000B FFFF Reserved area (256 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 60 ADDRESS SPACE 3.1 Outline of Address Space Extended external <Logical address space of M32170F4> area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (512 Kbytes) (16 Mbytes) (Note 1) H'0007 FFFF Reserved area (512 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 61 ADDRESS SPACE 3.1 Outline of Address Space Extended external <Logical address space of M32170F3> area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (384 Kbytes) (16 Mbytes) (Note 1) H'0005 FFFF Reserved area (640 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 62 ADDRESS SPACE 3.2 Operation Modes 3.2 Operation Modes The 32170 is placed in one of the following modes by setting its operation mode (using MOD0 and MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section 6.5, "Programming of Internal Flash Memory."...
Page 63 ADDRESS SPACE 3.2 Operation Modes Non-CS0 area H'0000 0000 Internal ROM Internal ROM area area (512 Kbytes) (512 Kbytes) H'0007 FFFF H'0008 0000 Reserved area (512 Kbytes) CS0 area H'000F FFFF (2 Mbytes) H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 CS1 area CS1 area...
Page 64 ADDRESS SPACE 3.3 Internal ROM/Extended External Area 3.3 Internal ROM Area and Extended External Area The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the internal ROM and extended external areas. Of this, a 4 Mbytes of address space from H'0000 0000 to H'0003 FFFF is the area that the user can actually use.
Page 65: Internal Ram Area And Sfr Area
ADDRESS SPACE 3.4 Internal ROM/SFR Area 3.4 Internal RAM Area and SFR Area The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of address space from H'0080 0000 to H'0081 FFFF is the area that the user can actually use.
Page 66 ADDRESS SPACE 3.4 Internal ROM/SFR Area H'0080 0000 SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 Pseudo-flash emulation areas separated in units of Internal RAM 8 Kbytes or 4 Kbytes can (32 Kbytes) be allocated here. For details, refer to Section 6.7. H'0080 BFFF Figure 3.4.2 Internal RAM Area and Special Function Register (SFR) Area of the M32170F4 and M32170F3...
Page 67 ADDRESS SPACE 3.4 Internal ROM/SFR Area +0 address +1 address +0 address +1 address H'0080 0000 H'0080 078C MJT (TID0) H'0080 078E Multijunction timer H'0080 0790 Interrupt (MJT) controller (ICU) MJT (TOD0) H'0080 07DE H'0080 007E H'0080 07E0 H'0080 0080 A-D0 converter Flash control H'0080 00EE...
Page 68 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 H'0080 0004 Interrupt Mask Register (IMASK) H'0080 0006 SBI Control Register (SBICR) TML1 Input Interrupt Control Register (ITML1CR) H'0080 0060 CAN0 Transmit/Receive &...
Page 69 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 00D2 8-bit A-D0 Data Register 1 (AD08DT1) H'0080 00D4 8-bit A-D0 Data Register 2 (AD08DT2) H'0080 00D6 8-bit A-D0 Data Register 3 (AD08DT3) H'0080 00D8 8-bit A-D0 Data Register 4 (AD08DT4) H'0080 00DA 8-bit A-D0 Data Register 5 (AD08DT5) H'0080 00DC...
Page 70 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0216 TIN Input Processing Control Register 2 (TINCR2) H'0080 0218 TIN Input Processing Control Register 3 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 (TINCR4) H'0080 021C H'0080 021E H'0080 0220...
Page 71 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0296 TOP5 Correction Register (TOP5CC) H'0080 0298 H'0080 029A TOP0-5 Control Register 0 (TOP05CR0) H'0080 029C TOP0-5 Control Register 1 (TOP05CR1) H'0080 029E H'0080 02A0 TOP6 Counter (TOP6CT) H'0080 02A2 TOP6 Reload Register (TOP6RL) H'0080 02A4...
Page 72 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 031C TIO0-3 Control Register 1 (TIO03CR1) H'0080 0320 TIO2 Counter (TIO2CT) H'0080 0322 H'0080 0324 TIO2 Reload 1 Register (TIO2RL1) H'0080 0326 TIO2 Reload 0/Measure Register (TIO2RL0) H'0080 0330 TIO3 Counter (TIO3CT) H'0080 0332...
Page 73 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 03BC TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) H'0080 03BE H'0080 03C0 TMS0 Counter (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register (TMS0MR1)
Page 74 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 DMA2 Transfer Count Register (DM2TCT) H'0080 0430 DMA2 Channel Control Register (DM2CNT) H'0080 0432 DMA2 Source Address Register (DM2SA) H'0080 0434 DMA2 Destination Address Register (DM2DA) H'0080 0436 DMA7 Transfer Count Register (DM7TCT) H'0080 0438 DMA7 Channel Control Register (DM7CNT)
Page 75 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0716 P22 Data Register (P22DATA) P1 Direction Register (P1DIR) H'0080 0720 P0 Direction Register (P0DIR) P3 Direction Register (P3DIR) P2 Direction Register (P2DIR) H'0080 0722 P4 Direction Register (P4DIR) H'0080 0724 P7 Direction Register (P7DIR) H'0080 0726...
Page 76 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 07B0 TOD0_4 Counter (TOD04CT) H'0080 07B2 H'0080 07B4 TOD0_4 Reload 1 Register (TOD04RL1) H'0080 07B6 TOD0_4 Reload 0 Register (TOD04RL0) H'0080 07B8 TOD0_5 Counter (TOD05CT) H'0080 07BA H'0080 07BC TOD0_5 Reload 1 Register (TOD05RL1) H'0080 07BE...
Page 77 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0A80 A-D1 Single Mode Register 0 (AD1SIM0) A-D1 Single Mode Register 1 (AD1SIM1) H'0080 0A82 H'0080 0A84 A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Scan Mode Register 1 (AD1SCM1) H'0080 0A86 H'0080 0A88 A-D1 Successive Approximation Register (AD1SAR)
Page 78 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0B96 TOD1_0 Reload 0 Register (TOD10RL0) H'0080 0B98 TOD1_1 Counter (TOD11CT) H'0080 0B9A H'0080 0B9C TOD1_1 Reload 1 Register (TOD11RL1) H'0080 0B9E TOD1_1 Reload 0 Register (TOD11RL0) TOD1_2 Counter (TOD12CT) H'0080 0BA0 H'0080 0BA2...
Page 79 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 TOM0_1 Reload 0 Register (TOM01RL0) H'0080 0C9E H'0080 0CA0 TOM0_2 Counter (TOM02CT) H'0080 0CA2 H'0080 0CA4 TOM0_2 Reload 1 Register (TOM02RL1) H'0080 0CA6 TOM0_2 Reload 0 Register (TOM02RL0) H'0080 0CA8 TOM0_3 Counter (TOM03CT) H'0080 0CAA...
Page 80 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 1000 CAN0 Control Register (CAN0CNT) H'0080 1002 CAN0 Status Register (CAN0STAT) H'0080 1004 CAN0 Extension ID Register (CAN0EXTID) H'0080 1006 CAN0 Configuration Register (CAN0CONF) H'0080 1008 CAN0 Time Stamp Count Register (CAN0TSTMP) H'0080 100A CAN0 Transmit Error Count Register (CAN0TEC)
Page 81 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) H'0080 1100 H'0080 1102 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) H'0080 1104 CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2)
Page 82 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 1154 CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) H'0080 1156 CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) H'0080 1158 CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 2 (C0MSL5DT2)
Page 83 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 CAN0 Message Slot 10 Data 3 (C0MSL10DT3) H'0080 11A8 CAN0 Message Slot 10 Data 2 (C0MSL10DT2) H'0080 11AA CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) H'0080 11AC CAN0 Message Slot 10 Data 6 (C0MSL10DT6) CAN0 Message Slot 10 Data 7 (C0MSL10DT7)
Page 84: Eit Vector Entry
ADDRESS SPACE 3.5 EIT Vector Entry 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/extended external areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here.
Page 85: Icu Vector Table
ADDRESS SPACE 3.6 ICU Vector Table 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set at the ad- dresses shown below.
Page 86 ADDRESS SPACE 3.6 ICU Vector Table Address +0 Address +1 Address DMA0-4 Interrupt Handler Start Address (A0-A15) H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA SIO1 Receive Interrupt Handler Start Address (A0-A15) H'0000 00CC H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16-A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31)
Page 87: Note About Address Space
ADDRESS SPACE 3.7 Notes on Address Space 3.7 Note about Address Space • Virtual flash emulation function The 32170 has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4 and M32170F3) into internal flash memory areas divided in 8 Kbytes (L banks).
Page 88 ADDRESS SPACE 3.7 Notes on Address Space This is a blank page. 3-32 Ver.0.10...
Page 89: Chapter 4 Eit
CHAPTER 4 CHAPTER 4 Outline of EIT EIT Event EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing 4.10 Trap Processing 4.11 EIT Priority Levels 4.12 Example of EIT Processing...
Page 90 4.1 Outline of EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt, and Trap). (1) Exception This is an event related to the context being executed.
Page 91: Eit Event
4.2 EIT Event 4.2 EIT Event 4.2.1 Exception (1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions.
Page 92: Eit Processing Procedure
4.3 EIT Processing Procedure 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. EIT request generated Program execution restarted...
Page 93 4.3 EIT Processing Procedure When an EIT is accepted, the M32R/E saves the PC and PSW (as will be described later) and branches to the EIT vector. The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch address) for the EIT handler is written.
Page 94: Eit Processing Mechanism
4.4 EIT Processing Mechanism 4.4 EIT Processing Mechanism The M32R/E's EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC register and the BPSW field of the PSW register). The M32R/E's internal EIT processing mechanism is shown below.
Page 95: Acceptance Of Eit Event
4.5 Acceptance of EIT Events 4.5 Acceptance of EIT Event When an EIT event occurs, the M32R/E suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below.
Page 96: Saving And Restoring The Pc And Psw
4.6 Saving and Restoring the PC and PSW 4.6 Saving and Restoring the PC and PSW The following describes operation of the M32R at the time when it accepts an EIT and when it executes the "RTE" instruction. (1) Hardware preprocessing when an EIT is accepted Save the SM, IE, and C bits of the PSW register ←...
Page 97 4.6 Saving and Restoring the PC and PSW Save SM, IE, and C bits Save PC Set vector address in PC Vector address Update SM, IE, and C bits Unchanged/0 Restore BSM, BIE, and BC bits Restore PC value from BPC from backup bits The value of BPC after execution of the "RTE"...
Page 98: Eit Vector Entry
4.7 EIT Vector Entry 4.7 EIT Vector Entry The EIT vector entry is located in the user space starting from address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address Reset Interrupt H'0000 0000 (Note 1) Indeterminate...
Page 99: Exception Processing
4.8 Exception Processing 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) [Occurrence Conditions] Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction which generated it is not executed.
Page 100 4.8 Exception Processing Address Address H'00 H'00 Return H'04 RIE occurred Return H'04 RIE occurred address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0020 in the user space.
Page 101: Address Exception (Ae)
4.8 Exception Processing 4.8.2 Address Exception (AE) [Occurrence Conditions] Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur: •...
Page 102 4.8 Exception Processing Address Address H'00 H'00 Return AE occurred Return AE occurred H'04 H'04 address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0030 in the user space.
Page 103: Interrupt Processing
4.9 Interrupt Processing 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) [Occurrence Conditions] ____________ Reset Interrupt (RI) is unconditionally accepted in any machine cycle by pulling the RESET input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE, and C bits The SM, IE, and C bits of the PSW register are initialized in the manner shown below.
Page 104: System Break Interrupt (Sbi)
4.9 Interrupt Processing 4.9.2 System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected.
Page 105 4.9 Interrupt Processing [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits-the BSM, BIE, and BC bits. ← SM ← IE ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below.
Page 106: External Interrupt (Ei)
4.9 Interrupt Processing 4.9.3 External Interrupt (EI) An external interrupt is generated upon an interrupt request which is output by the 32170's internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, refer to Chapter 5, "Interrupt Controller." For details about the interrupt sources, refer to each section in which the relevant internal peripheral I/O is described.
Page 107 4.9 Interrupt Processing [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. ← SM ← IE ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below.
Page 108: Trap Processing
4.10 Trap Processing 4.10 Trap Processing 4.10.1 Trap (TRAP) [Occurrence Conditions] Traps refer to software interrupts which are generated by executing the "TRAP" instruction. Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands 0-15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits –...
Page 109 4.10 Trap Processing Address Address H'00 H'00 H'04 H'04 TRAP occurred TRAP occurred Return Return H'08 H'08 address address H'0C H'0C H'08 H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to the addresses H'0000 0040 through H'0000 007C in the user space.
Page 110: Eit Priority Levels
4.11 EIT Priority Levels 4.11 EIT Priority Levels The table below lists the priority levels of EIT events. When multiple EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing...
Page 111: Example Of Eit Processing
4.12 Example of EIT Processing 4.12 Example of EIT Processing (1) When RIE, AE, SBI, EI, or TRAP occurs singly IE=1 BPC register = Return address A IE=0 RIE, AE, SBI, EI, If IE = 0, no events but reset or TRAP occurrs Singly and SBI are accepted Return address A:...
Page 112 4.12 Example of EIT Processing EIT vector entry BRA instruction (Any event other than SBI) (SBI) EIT handler Save BPC to stack Hardware (B)PSW preprocessing Save PSW to stack System Break Interrupt processing Save general-purpose Program registers to stack being executed •...
Page 113: Chapter 5 Interrupt Controller (Icu)
CHAPTER 5 CHAPTER 5 INTERRUPT CONTROLLER (ICU) Outline of the Interrupt Controller (ICU) Interrupt Sources of Internal Peripheral I/Os ICU-Related Registers ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation...
Page 114: Outline Of Interrupt Controller (Icu)
INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.1 Outline of Interrupt Controller (ICU) The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as external interrupts (EI).
Page 115 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) Interrupt controller System Break Interrupt request generated SBI Control Register SBIREQ (SBICR) the CPU core Peripheral circuits Interrupt Edge- recognized request IREQ Maskable interrupt Edge- ILEVEL Interrupt recognized request generated request IREQ Edge-...
Page 116: Interrupt Sources Of Internal Peripheral I/Os
INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os 5.2 Interrupt Sources of Internal Peripheral I/Os The interrupt controller receives as its inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD, and CAN. For details about these interrupts, refer to each section in which the relevant internal peripheral I/O is described.
Page 117 INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os Table 5.2.2 Interrupt Sources of Internal Peripheral I/Os (2/2) Interrupt Source Content Number of Input ICU Type of Input Sources Source (Note) MJT output interrupt 7 MJT output interrupt group 7 (TMS0, TMS1 output) Level-recognized MJT output interrupt 6 MJT output interrupt group 6 (TOP8, TOP9 output)
Page 118: Icu-Related Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3 ICU-Related Registers The diagram below shows a map of the Interrupt Controller (ICU)'s related registers. Address +0 Address +1 Address H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 Interrupt Mask Register (IMASK) H'0080 0004 SBI Control Register (SBICR) H'0080 0006 TML1 Input Interrupt Control Register...
Page 119: Interrupt Vector Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.1 Interrupt Vector Register Interrupt Vector Register (IVECT) <Address:H'0080 0000> IVECT <When reset: Indeterminate> Bit Name Function 0 – 15 IVECT (16 low-order When an interrupt is accepted, the 16 low-order bits – bits of ICU vector in ICU vector table address for the accepted table address) interrupt source is stored in this register.
Page 120: Interrupt Mask Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.2 Interrupt Mask Register Interrupt Mask Register (IMASK) <Address:H'0080 0004> IMASK <When reset: H''07> Bit Name Function 0 – 4 No functions assigned – 5– 7 IMASK (Interrupt mask) 000 : Maskable interrupts are disabled 001 : Level 0 interrupts can be accepted 010 : Level 0-1 interrupts can be accepted 011 : Level 0-2 interrupts can be accepted...
Page 121: Sbi (System Break Interrupt) Control Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.3 SBI (System Break Interrupt) Control Register SBI (System Break Interrupt) Control Register <Address:H'0080 0006> SBIREQ <When reset: H''00> Bit Name Function 0 – 6 No functions assigned – SBI REQ (SBI request) 0 : SBI is not requested 1 : SBI is requested : Writable for only clearing operation (see the description below) _______...
Page 122: Interrupt Control Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.4 Interrupt Control Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) <Address:H'0080 0060> TML1 Interrupt Control Register (ITML1CR) <Address:H'0080 0061> TID2 Output Interrupt Control Register (ITID2CR) <Address:H'0080 0062> A-D1 Converter Interrupt Control Register (IAD1CCR) <Address:H'0080 0063>...
Page 123 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers D15) IREQ ILEVEL <When reset: H''07> Bit Name Function 0 – 2 No functions assigned – (8-10) IREQ (Interrupt request) 0 : Interrupt is not requested (11) 1 : Interrupt is requested No functions assigned –...
Page 124 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers Interrupt request from each peripheral function IREQ D3,11 set/clear Data bus Interrupt enabled D5-7,13-15 ILEVEL Interrupt priority (Levels 0-7) resolving circuit Figure 5.3.2 Interrupt Control Register Configuration (Edge-recognized Type) Group Interrupt request from each Group interrupt peripheral function Read-only circuit...
Page 125 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers (2) ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to enable interrupts.
Page 126: Icu Vector Table
INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 31-source interrupts are assigned the following addresses: Table 5.4.1 ICU Vector Table Addresses Interrupt Source ICU Vector Table Address MJT Input Interrupt 4...
Page 127 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 Address +1 Address MJT Input Interrupt 4 Handler Start Address (A0-A15) H'0000 0094 MJT Input Interrupt 4 Handler Start Address (A16-A31) H'0000 0096 MJT Input Interrupt 3 Handler Start Address (A0-A15) H'0000 0098 MJT Input Interrupt 3 Handler Start Address (A16-A31) H'0000 009A...
Page 128 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 Address +1 Address DMA0-4 Interrupt Handler Start Address (A0-A15) H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA SIO1 Receive Interrupt Handler Start Address (A0-A15) H'0000 00CC H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16-A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31)
Page 129: Description Of Interrupt Operation
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set by the Interrupt Control Register and the IMASK value of the Interrupt Mask Register.
Page 130 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.1 Hardware-fixed Priority Levels Priority Interrupt Source ICU Vector Table Address Type of Input Source High MJT Input Interrupt 4 (IRQ12) H'0000 0094-H'0000 0097 Level-recognized MJT Input Interrupt 3 (IRQ11) H'0000 0098-H'0000 009B Level-recognized MJT Input Interrupt 2 (IRQ10) H'0000 009C-H'0000 009F...
Page 131 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL="000") Accepted when IMASK is 1-7 1 (ILEVEL="001") Accepted when IMASK is 2-7 2 (ILEVEL="010") Accepted when IMASK is 3-7 3 (ILEVEL="011")
Page 132: Processing Of Internal Peripheral I/O Interrupts By Handlers
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing of Internal Peripheral I/O Interrupts by Handlers (1) Branching to the interrupt handler When the CPU accepts an interrupt, control branches to the EIT vector entry after hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for External Interrupt (EI) is located at address H'0000 0080.
Page 133 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation EI (External Interrupt) vector entry H'0000 0080 BRA instruction EI (External Interrupt) handler Save BPC to stack Save PSW to stack (Note) Save general-purpose Program register to stack being executed Read Interrupt Mask IMASK H'0080 0004 Register (IMASK) and...
Page 134: Description Of System Break Interrupt (Sbi) Operation
INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation 5.6.1 Acceptance of SBI System Break Interrupt (SBI) is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is _______ accepted anytime upon detection of a falling edge on the SBI signal regardless of how the PSW register IE bit is set, and cannot be masked.
Page 135: Chapter 6 Internal Memory
CHAPTER 6 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.2 Internal RAM 6.3 Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.6 Boot ROM 6.7 Virtual Flash Emulation Function 6.8 Connecting to A Serial Programmer...
Page 136 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.1 Outline of the Internal Memory The 32170 internally contains the following types of memory: • 40 Kbyte or 32 Kbyte RAM • 768 Kbyte, 512 Kbyte, or 384 Kbyte flash memory 6.2 Internal RAM Specifications of the 32170's internal RAM are shown below.
Page 137 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory The diagram below shows a register map associated with the internal flash memory. Address +0 Address +1 Address Flash Mode Register Flash Status Register 1 H'0080 07E0 (FMOD) (FSTAT1)
Page 138: Flash Mode Register
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.1 Flash Mode Register Flash Mode Register (FMOD) <Address: H'0080 07E0> FPMOD <When reset : H'0?> Bit Name Function 0 - 6 No functions assigned — FPMOD 0 : FP pin = low —...
Page 139: Flash Status Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.2 Flash Status Registers The 32170 has two registers to indicate the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address: H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself.
Page 140 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Status Register 2 (FSTAT2) FBUSY ERASE WRERR1 WRERR2 <When reset : H'80> Bit Name Function FBUSY 0 : Program or erase under way — (Flash busy) 1 : Ready state No functions assigned —...
Page 141 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory (4) WRERR2 (Program operating condition) bit (D12) The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error. When WRERR2 = 0, it means the program operation terminated normally;...
Page 142: Flash Controle Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.3 Flash Controle Registers Flash Controle Register 1 (FCNT1) <Address: H'0080 07E2> FENTRY FEMMOD <When reset : H'00> Bit Name Function 0 - 2 No functions assigned — FENTRY 0 : Normal read (Flash mode entry) 1 : Erase/program enable 4 - 6...
Page 143 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is located at address H'0000 0080 of the flash memory. When running a flash rewrite program in RAM while the FENTRY bit = 1, the EI vector entry is located at address H'0080 4000 of the RAM, allowing for flash rewrite operation to be controlled using interrupts.
Page 144 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 2 (FCNT2) <Address: H'0080 07E3> FPROT <When reset : H'00> Bit Name Function 8 - 14 No functions assigned — FPROT 0 : Protection by lock bit effective (Unlock) 1 : Protection by lock bit not effective The Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection...
Page 145 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 3 (FCNT3) <Address: H'0080 07E4> FELEVEL <When reset : H'00> Bit Name Function 0 - 6 No functions assigned — FELEVEL 0 : Normal level (Raise erase margin) 1 : Raise erase margin The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands.
Page 146 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 4 (FCNT4) <Address: H'0080 07E5> FRESET <When reset : H'00> Bit Name Function 8 - 14 No functions assigned — FRESET 0 : No operation performed (Reset flash) 1 : Reset the flash memory The Flash Control Register 4 (FCNT4) controls canceling program/erase operation in the middle and initializing each status bit of Flash Status Register 2 (FSTAT2).
Page 147 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory FENTRY=0 FENTRY=1 Program/erase flash memory Error found Program/erase terminated normally FRESET=1 FRESET=0 Program/erase flash memory Figure 6.4.3 Example for Using the FCNT4 Register 6-13 Ver.0.10...
Page 148: Virtual Flash L Bank Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.4 Virtual Flash L Bank Registers Virtual Flash L Bank Register 0 (FELBANK0) <Address: H'0080 07E8> Virtual Flash L Bank Register 1 (FELBANK1) <Address: H'0080 07EA> Virtual Flash L Bank Register 2 (FELBANK2) <Address: H'0080 07EC>...
Page 149: Virtual Flash S Bank Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.5 Virtual Flash S Bank Registers Virtual Flash S Bank Register 0 (FESBANK0) <Address: H'0080 07F0> Virtual Flash S Bank Register 1 (FESBANK1) <Address: H'0080 07F2> SBANKAD <When reset : H'0000> Bit Name Function MODENS...
Page 150: Programming Of The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.5.1 Outline of Programming Flash Memory When writing to the internal flash memory, there are following two methods to use depending on situation: (1) When the write program does not exist in the internal flash memory (2) When the write program already exists in the internal flash memory For (1), set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot flash E/W enable mode.
Page 151 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash E/W enable mode Normal mode (FENTRY=1) (FENTRY=0) H'0000 0000 H'0000 0000 EI vector entry (H'0000 0080) Internal ROM area Internal ROM area EI vector entry H'0080 3FFF H'0080 3FFF (H'0080 4000) H'0080 4000 H'0080 4000 Internal RAM...
Page 152 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (1) When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to write to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode.
Page 153 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Reset deasserted (Boot program starts) Reset deasserted Mode selected Mode selected POWER ON RESET MOD0 MOD1 Settings by boot program FENTRY Writes to flash memory by boot program Figure 6.5.3 Internal Flash Memory Write Timings (when the write program does not exist in the flash memory) 6-19 Ver.0.10...
Page 154 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) When the write program already exists in the internal flash memory Use the flash write program already stored in the internal flash memory to write to the flash memory. For write to the flash memory, use the internal peripheral circuits according to your programming system.
Page 155 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash mode Flash rewrite Flash mode turned off starts turned on RESET "H" or "L" "L" MOD0 "H" or "L" (Single-chip or extended external) MOD1 "H" or "L" FENTRY Write to flash memory by flash rewrite program Flash rewrite program transferred to RAM...
Page 156: Controlling Operation Mode During Programming Flash
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.2 Controlling Operation Mode during Programming Flash The device's operation modes are set by MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be set during flash write. Table 6.5.1 Operation Modes Set during Flash Write MOD0 MOD1 FENTRY Operation Mode...
Page 157 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) Entering flash E/W enable mode Flash E/W enable mode can be entered only when the device is operating in single-chip mode or extended external mode. Namely, you can enter flash E/W enable mode only when the FP pin = high and the Flash Control Register 1 (FCNT1) FENTRY bit = 1.
Page 158 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Enter one of the following modes: • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode FMOD(H'0080 07E0) • Extended external mode + flash E/W FPMOD enable mode P8DATA(H'0080 0708)
Page 159: Programming Procedure To The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.3 Programming Procedure to the Internal Flash Memory To write to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal RAM.
Page 160 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) Page Program command Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write.
Page 161 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.3 M32170F6 Target Blocks and Specified Addresses Target Block Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE...
Page 162 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.5 M32170F3 Target Blocks and Specified Addresses Target Block Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE 6-28 Ver.0.10...
Page 163 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F6's Internal Flash Memory Area (768KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF H'0000 6000 Block 2 H'0000 7FFF Uneven blocks H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 164 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F4's Internal Flash Memory Area (512KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF Uneven blocks H'0000 6000 Block 2 H'0000 7FFF H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 165 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F3's Internal Flash Memory Area (384KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF Uneven blocks H'0000 6000 Block 2 H'0000 7FFF H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 166 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (4) Block Erase command The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to erase (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses").
Page 167 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (8) Read Lock Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory.
Page 168 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command...
Page 169 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Page Program command (H'4141) to any address of internal flash memory. Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address.
Page 170 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 171 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 172 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 173 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any address of internal flash memory. Figure 6.5.15 Read Status Register START Write Clear Status command (H'5050) to any address of internal flash memory.
Page 174: Flash Write Time (For Reference)
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.4 Flash Write Time (for Reference) The time required for writing to the internal flash memory is shown below for your reference. (1) M32170F6 Transfer time by SIO (for a transfer data size of 768 KB) 1/57600 bps ×...
Page 175 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (3) M32170F3 Transfer time by SIO (for a transfer data size of 384 KB) 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 384 KB 75.1 [s] Flash write time 384 KB/256-byte block ×...
Page 176: Boot Rom
INTERNAL MEMORY 6.6 Boot ROM 6.6 Boot ROM The table below shows boot memory specifications of the 32170. Table 6.6.1 Boot Memory Specifications Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait states (with 40 MHz internal CPU memory clock) Internal bus connection Connected by 32-bit bus Read...
Page 177: Virtual Flash Emulation Function
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7 Virtual Flash Emulation Function The 32170 has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4 and M32170F3) into the internal flash memory area divided in units of 8 Kbytes (L banks).
Page 178 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes H'0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H'0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes RAM bank S block 0 H'0080 A000 (FESBANK0) 4 Kbytes...
Page 179: Virtual Flash Emulation Area
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.1 Virtual Flash Emulation Area The following shows the areas for which the Virtual Flash Emulation Function is effective. The Virtual Flash L Bank Registers (FELBANK0 to FELBANK3 for the M32170F6, FELBANK0 to FELBANK2 for the M32170F4 and M32170F3) allow one among all L banks of flash memory divided in 8 Kbytes each to be selected by setting the seven bits A12-A18 of the start address of the desired L bank in the Virtual Flash L Bank Register LBANKAD bits.
Page 180 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function <Internal flash> H'0000 0000 L bank 0 (8 Kbytes) <Internal RAM> L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes H'0080 A000...
Page 181 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function <Internal flash> H'0000 0000 L bank 0 (8 Kbytes) <Internal RAM> L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes...
Page 182 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function <Internal flash> H'0000 0000 L bank 0 (8 Kbytes) <Internal RAM> L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes...
Page 183 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 94 H'000B C000...
Page 184 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 62 H'0007 C000...
Page 185 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 46 H'0005 C000...
Page 186: Entering Virtual Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.2 Entering Virtual Flash Emulation Mode To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function.
Page 187: Application Example Of Virtual Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.3 Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx...
Page 188 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function (4) Program operation using RAM block 1 Flash Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 Data write to RAM0 RAM block 1 (5) Program operation changed from RAM block 1 to RAM block 0 Flash Replace Bank xx...
Page 189: Connecting To A Serial Programmer
INTERNAL MEMORY 6.8 Connecting to A Serial Programmer 6.8 Connecting to A Serial Programmer When you rewrite the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32170 shown below to make them suitable for the serial programmer.
Page 190 INTERNAL MEMORY 6.8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur.
Page 191: Precautions To Be Taken When Rewriting Flash Memory
INTERNAL MEMORY 6.9 Precautions to Be Taken When Rewriting Flash Memory 6.9 Precautions to Be Taken When Rewriting Flash Memory The following describes precautions to be taken when you rewrite the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. •...
Page 192 INTERNAL MEMORY 6.9 Precautions to Be Taken When Rewriting Flash Memory This is a blank page. 6-58 Ver.0.10...
Page 193: Outline Of Reset
CHAPTER 7 CHAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State Immediately after Reset Release 7.4 Things To Be Considered after Reset Release...
Page 194: Reset At Power-On
RESET 7.1 Outline of Reset 7.1 Outline of Reset _____ The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out _____ of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry.
Page 195: Internal State Immediately After Reset Release
RESET 7.3 Internal State Immediately after Reset Release 7.3 Internal State Immediately after Reset Release The table below lists the register state of the device immediately after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described.
Page 196: Things To Be Considered After Reset Release
RESET 7.4 Things To Be Considered after Reset Release 7.4 Things To Be Considered after Reset Release • Input/output ports After reset release, the 32170's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit.
Page 197: Outline Of Input/Output Ports
CHAPTER 8 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits...
Page 198 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32170 has a total of 157 input/output ports from P0 to P22 (of which P5 is reserved for future use, however). These input/output ports can be set for input or output mode by a direction register. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line.
Page 199 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 157 lines P00 - P07 (8 lines) P10 - P17 (8 lines) P20 - P27 (8 lines) P30 - P37 (8 lines) P41 - P47 (7 lines)
Page 200 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions).
Page 201 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions DB10 DB11 DB12 DB13 DB14 DB15 Settings of CPU operation mode (Note 1) BLW/ BHW/ (Reserved) SCLKI4/ SCLKI5/ (P61) (P62) (P63) ADTRG SCLKO4 SCLKO5 BCLK/ WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK SCLKI0/ SCLKI1/ TXD0...
Page 202 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers Included in the 32170 as input/output port related registers are the Port Data Registers, Port Direction Registers, and Port Operation Mode Registers. Of these, the Port Operation Mode Registers are provided for only P6-P22.
Page 203 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +1 Address +0 Address Address H'0080 0744 Port Input Function Enable Register (PIEN) P6 Operation Mode Register (P6MOD) P7 Operation Mode Register (P7MOD) H'0080 0746 P8 Operation Mode Register (P8MOD) H'0080 0748 P9 Operation Mode Register (P9MOD) P10 Operation Mode Register (P10MOD)
Page 204: Port Data Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.1 Port Data Registers P0 Data Register (P0DATA) <Address: H'0080 0700> P1 Data Register (P1DATA) <Address: H'0080 0701> P2 Data Register (P2DATA) <Address: H'0080 0702> P3 Data Register (P3DATA) <Address: H'0080 0703> P4 Data Register (P4DATA) <Address: H'0080 0704>...
Page 205 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers <When reset : Indeterminate> Bit Name Function Pn0DT (Port Pn0 data) Depending on how the Port Direction Register is set Pn1DT (Port Pn1 data) • When direction bit = 0 (input mode) Pn2DT (Port Pn2 data) 0: Port input pin = low Pn3DT (Port Pn3 data)
Page 206: Port Direction Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) <Address: H'0080 0720> P1 Direction Register (P1DIR) <Address: H'0080 0721> P2 Direction Register (P2DIR) <Address: H'0080 0722> P3 Direction Register (P3DIR) <Address: H'0080 0723> P4 Direction Register (P4DIR) <Address: H'0080 0724>...
Page 207 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers <When reset : H'00> Bit Name Function Pn0DIR (Port Pn0 direction bit) 0: Input mode (when reset) Pn1DIR (Port Pn1 direction bit) 1: Output mode Pn2DIR (Port Pn2 direction bit) Pn3DIR (Port Pn3 direction bit) Pn4DIR (Port Pn4 direction bit) Pn5DIR (Port Pn5 direction bit)
Page 208: Port Operation Mode Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers P6 Operation Mode Register (P6MOD) <Address: H'0080 0746> P65MOD P66MOD P67MOD <When reset : H'00> Bit Name Function 0 - 4 No functions assigned — P65MOD 0 : P65 (Port P65 operation mode)
Page 209 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset : H'00> Bit Name Function P70MOD 0 : P70 (Port P70 operation mode) 1 : BCLK / WR P71MOD 0 : P71...
Page 210 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P8 Operation Mode Register (P8MOD) <Address: H'0080 0748> P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD <When reset : H'00> Bit Name Function 0, 1 No functions assigned — P82MOD 0 : P82 (Port P82 operation mode) 1 : TXD0 P83MOD...
Page 211 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P9 Operation Mode Register (P9MOD) <Address: H'0080 0749> P93MOD P94MOD P95MOD P96MOD P97MOD <When reset : H'00> Bit Name Function 8 - 10 No functions assigned — P93MOD 0 : P93 (Port P93 operation mode) 1 : TO16 P94MOD...
Page 212 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P10 Operation Mode Register (P10MOD) <Address: H'0080 074A> P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD <When reset : H'00> Bit Name Function P100MOD 0 : P100 (Port P100 operation mode) 1 : TO8 P101MOD 0 : P101...
Page 213 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P11 Operation Mode Register (P11MOD) <Address: H'0080 074B> P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD <When reset : H'00> Bit Name Function P110MOD 0 : P110 (Port P110 operation mode) 1 : TO0 P111MOD 0 : P111...
Page 214 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P12 Operation Mode Register (P12MOD) <Address: H'0080 074C> P124MOD P125MOD P126MOD P127MOD <When reset : H'00> Bit Name Function 0 - 3 No functions assigned — P124MOD 0 : P124 (Port P124 operation mode) 1 : TCLK0 P125MOD...
Page 215 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P13 Operation Mode Register (P13MOD) <Address: H'0080 074D> P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD <When reset : H'00> Bit Name Function P130MOD 0 : P130 (Port P130 operation mode) 1 : TIN16 P131MOD 0 : P131...
Page 216 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P14 Operation Mode Register (P14MOD) <Address: H'0080 074E> P140MOD P141MOD P142MOD P143MOD P144MOD P145MOD P146MOD P147MOD <When reset : H'00> Bit Name Function P140MOD 0 : P140 (Port P140 operation mode) 1 : TIN8 P141MOD 0 : P141...
Page 217 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P15 Operation Mode Register (P15MOD) <Address: H'0080 074F> P150MOD P151MOD P152MOD P153MOD P154MOD P155MOD P156MOD P157MOD <When reset : H'00> Bit Name Function P150MOD 0 : P150 (Port P150 operation mode) 1 : TIN0 P151MOD 0 : P151...
Page 218 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P16 Operation Mode Register (P16MOD) <Address: H'0080 0750> P160MOD P161MOD P162MOD P163MOD P164MOD P165MOD P166MOD P167MOD <When reset : H'00> Bit Name Function P160MOD 0 : P160 (Port P160 operation mode) 1 : TO21 P161MOD 0 : P161...
Page 219 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P17 Operation Mode Register (P17MOD) <Address: H'0080 0751> P172MOD P173MOD P174MOD P175MOD P176MOD P177MOD <When reset : H'00> Bit Name Function 8, 9 No functions assigned — P172MOD 0 : P172 (Port P172 operation mode) 1 : TIN24 P173MOD...
Page 220 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P18 Operation Mode Register (P18MOD) <Address: H'0080 0752> P180MOD P181MOD P182MOD P183MOD P184MOD P185MOD P186MOD P187MOD <When reset : H'00> Bit Name Function P180MOD 0 : P180 (Port P180 operation mode) 1 : TO29 P181MOD 0 : P181...
Page 221 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P19 Operation Mode Register (P19MOD) <Address: H'0080 0753> P190MOD P191MOD P192MOD P193MOD P194MOD P195MOD P196MOD P197MOD <When reset : H'00> Bit Name Function P190MOD 0 : P190 (Port P190 operation mode) 1 : TIN26 P191MOD 0 : P191...
Page 222 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P20 Operation Mode Register (P20MOD) <Address: H'0080 0754> P200MOD P201MOD P202MOD P203MOD <When reset : H'00> Bit Name Function P200MOD 0 : P200 (Port P200 operation mode) 1 :TXD4 P201MOD 0 : P201 (Port P201 operation mode) 1 : RXD4...
Page 223 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P21 Operation Mode Register (P21MOD) <Address: H'0080 0755> P210MOD P211MOD P212MOD P213MOD P214MOD P215MOD P216MOD P217MOD <When reset : H'00> Bit Name Function P210MOD 0 : P210 (Port P210 operation mode) 1 : TO37 P211MOD 0 : P211...
Page 224 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> P220MOD P224MOD P225MOD <When reset : H'00> Bit Name Function P220MOD 0 : P220 (Port P220 operation mode) 1 : CTX 1 - 3 No functions assigned —...
Page 225 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Port Input Function Enable Register (PIEN) <Address: H'0080 0745> PIEN0 <When reset : H'00> Bit Name Function 8 - 14 No functions assigned — PIEN0 0 : Disables input (to prevent current from flowing in) (Port input function enable bit) 1 : Enables input This register is provided to prevent current from flowing into the port input pin.
Page 226 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Mode Name Controllable Pins Noncontrollable Pins P00 - P07, P10 - P17, P20 - P27 P64, P221, FP P30 -P37 , P41 - P47, P61 - P63 Single chip P65 - P67, P70 - P77, P82 - P87 P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137, P140 - P147 P150 - P157, P160 - P167, P172 - P177...
Page 227: Port Peripheral Circuits
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) Direction P20 - P27 (A23-A30) register P30 - P37 (A15-A22)
Page 228 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P64 (SBI) P221 / CRX Data bus (DB0 - DB15) Direction ____ P72 (HREQ) register Port output Data bus latch (DB0 - DB15) Operation mode register HREQ Input function enable Note : denotes pins.
Page 229 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits ____ P71 (WAIT) Direction register Port output Data bus latch (DB0 - DB15) Operation mode register WAIT Input function enable P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) Direction P76 (RTDACK) register P82 (TXD0) Data bus...
Page 230 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P84 (SCLKI0, SCLKO0) P87 (SCLKI1, SCLKO1) P65 (SCLKI14, SCLKO4) P66 (SCLKI15, SCLKO5) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function...
Page 231: Chapter 9 Dmac
CHAPTER 9 CHAPTER 9 DMAC 9.1 Outline of the DMAC 9.2 DMAC Related Registers 9.3 Functional Description of the DMAC 9.4 Precautions about the DMAC...
Page 232 DMAC 9.1 Outline of the DMAC 9.1 Outline of the DMAC The 32170 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O.
Page 233 DMAC 9.1 Outline of the DMAC DMA channel 0 Software start Source address register One DMA2 transfer completed Destination address A-D conversion completed request register MJT (TIO8_udf) selector Transfer count MJT (input event bus 2) register DMA channel 1 Software start Source MJT (output event bus 0) request...
Page 234 DMAC 9.2 DMAC Related Registers 9.2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers. +0 Address +1 Address Address DMA0-4 Interrupt Mask DMA0-4 Interrupt Request Status H'0080 0400 Register (DM04ITMK) Register (DM04ITST) DMA5-9 Interrupt Request Status DMA5-9 Interrupt Mask H'0080 0408 Register (DM59ITST)
Page 235 DMAC 9.2 DMAC Related Registers +0 Address +1 Address Address DMA3 Channel Control DMA3 Transfer Count H'0080 0440 Register (DM3CNT) Register (DM3TCT) H'0080 0442 DMA3 Source Address Register (DM3SA) H'0080 0444 DMA3 Destination Address Register (DM3DA) H'0080 0446 DMA8 Channel Control DMA8 Transfer Count H'0080 0448 Register (DM8CNT)
Page 236: Dma Channel Control Register
DMAC 9.2 DMAC Related Registers 9.2.1 DMA Channel Control Register DMA0 Channel Control Register (DM0CNT) <Address: H'0080 0410> MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 <When reset : H'00> Bit Name Function MDSEL0 0 : Normal mode (Selects DMA0 transfer mode) 1 : Ring buffer mode TREQF0 0 : Not requested...
Page 237 DMAC 9.2 DMAC Related Registers DMA1 Channel Control Register (DM1CNT) <Address: H'0080 0420> MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 <When reset : H'00> Bit Name Function MDSEL1 0 : Normal mode (Selects DMA1 transfer mode) 1 : Ring buffer mode TREQF1 0 : Not requested (DMA1 transfer request flag)
Page 238 DMAC 9.2 DMAC Related Registers DMA2 Channel Control Register (DM2CNT) <Address: H'0080 0430> MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 <When reset : H'00> Bit Name Function MDSEL2 0 : Normal mode (Selects DMA2 transfer mode) 1 : Ring buffer mode TREQF2 0 : Not requested (DMA2 transfer request flag)
Page 239 DMAC 9.2 DMAC Related Registers DMA3 Channel Control Register (DM3CNT) <Address: H'0080 0440> MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 <When reset : H'00> Bit Name Function MDSEL3 0 : Normal mode (Selects DMA3 transfer mode) 1 : Ring buffer mode TREQF3 0 : Not requested (DMA3 transfer request flag)
Page 240 DMAC 9.2 DMAC Related Registers DMA4 Channel Control Register (DM4CNT) <Address: H'0080 0450> MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 <When reset : H'00> Bit Name Function MDSEL4 0 : Normal mode (Selects DMA4 transfer mode) 1 : Ring buffer mode TREQF4 0 : Not requested (DMA4 transfer request flag)

Mitsubishi Electric M32R Series User Manual

Chapter 1 Overview

Chapter 3 Address Space

Chapter 4 Eit

Chapter 5 Interrupt Controller (Icu)

Chapter 6 Internal Memory

Chapter 9 Dmac

Chapter 10 Multijunction Timers

Chapter 11 A-D Converters

Chapter 12 Serial I/O

Chapter 13 Can Module

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Summary of Contents for Mitsubishi Electric M32R Series