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10
For interrupts which have two or more sources of interrupt in one interrupt table, interrupt control
registers are provided, with which to control interrupt requests and determine interrupt input.
Therefore, the status flags in the interrupt controller function only as a bit to show whether an
interrupt-enabled interrupt request occurred and cannot be written to.
(1) Interrupt request status bit
This status bit shows whether an interrupt request occurred. When an interrupt request is
generated, this bit is set in hardware (but cannot be set in software). The status bit is cleared by
writing a 0, but not affected by writing a 1, in which case the bit holds the status intact. Because
the status bit is unaffected by interrupt mask bits, it can also be used to check the operation of
peripheral function. In interrupt processing, make sure that among grouped interrupt flags, only
the flag for the serviced interrupt is cleared. Clearing flags for unserviced interrupts results in the
pending interrupt requests also being cleared.
(2) Interrupt mask bit
This bit is used to disable unnecessary interrupts among grouped interrupt requests. Set this bit
to 0 to enable interrupts or 1 to disable interrupts.
Group interrupt
Each timer or TIN input
Data bus
Figure 10.2.5 Interrupt Status Register and Mask Register
interrupt request
Set
Interrupt status
Data = 0
clear
F/F
F/F
Interrupt enable
10-38
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timer
Interrupt
controller
Ver.0.10
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