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11
The comparison result finally is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn)
corresponding to each converted channel. Also, the 8-bit A-D Data Register (AD08DTn, AD18DTn)
contains the 8 high-order bits of the 10-bit A-D conversion result.
The following shows the procedure for A-D conversion by successive approximation in each
operation mode.
(1) Single mode
The convert operation stops when comparison of the A-D Successive Approximation Register's
D15 bit is completed. The content (A-D conversion result) of the A-D Successive Approximation
Register is transferred to the 10-bit A-D Data Registers 0-15 for the converted channel.
(2) Single-shot scan mode
When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel
is completed, the content of the A-D Successive Approximation Register is transferred to the
corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (2) to (7) above
are reexecuted for the next channel to be converted.
In single-shot scan mode, the convert operation stops when A-D conversion for one specified
scan loop is completed.
(3) Continuous scan mode
When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel
is completed, the content of the A-D Successive Approximation Register is transferred to the
corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (2) to (7) above
are reexecuted for the next channel to be converted.
During continuous scan mode, the convert operation is executed continuously until scan
operation is forcibly halted by setting the A-D conversion stop bit (Scan Mode Register 0's D6 bit)
to 1.
11.3 Functional Description of A-D Converters
11-43
A-D CONVERTERS
Ver.0.10
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