12
Serial I/O
related
registers
Note : When you selected the clock divider's divide-by ratio = 1, you are subject to limitations that the
baud rate register value you set must be equal to or greater than 7.
Figure 12.7.1 Procedure for UART Receive Initialization
Initial settings for UART
reception
Set SIO Transmit/Receive Mode Register
Set SIO Transmit Control Register
Set SIO Baud Rate Register
Set SIO Interrupt Related Registers
Set the interrupt controller
SIO Receive Interrupt Control Register
Set DMAC related registers
Set input/output port
Operation Mode Register
Initial settings for UART
reception finished
12.7 Receive Operation in UART Mode
• Set register to UART mode
• Set parity (when enabled,
• Set stop bit length
• Set character length
• Select clock divider's divide-by ratio
• Divide-by ratio H'00 to H'FF (Note)
• Cause of Receive Interrupt
Select Register
(receive finished/receive error)
• Interrupt Mask Register
(enable/disable receive interrupts)
(When using interrupt)
(When using DMAC)
12-56
SERIAL I/O
select odd/even)
Ver.0.10