Eit Vector Entry - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers
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4

4.7 EIT Vector Entry

The EIT vector entry is located in the user space starting from address H'0000 0000. The table
below lists the EIT vector entry.
Table 4.7.1 EIT Vector Entry
Name
Reset Interrupt
System Break Interrupt SBI
Reserved Instruction
Exception
Address Exception
Trap
External Interrupt
Note 1: During boot mode, this vector address is moved to the beginning of the boot ROM (address H'8000
0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory."
Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM
(address H'0080 4000). For details, refer to Section 6.5, "Programming of Internal Flash Memory."
Abbreviation Vector Address
RI
H'0000 0000 (Note 1)
H'0000 0010
RIE
H'0000 0020
AE
H'0000 0030
TRAP0
H'0000 0040
TRAP1
H'0000 0044
TRAP2
H'0000 0048
TRAP3
H'0000 004C
TRAP4
H'0000 0050
TRAP5
H'0000 0054
TRAP6
H'0000 0058
TRAP7
H'0000 005C
TRAP8
H'0000 0060
TRAP9
H'0000 0064
TRAP10
H'0000 0068
TRAP11
H'0000 006C
TRAP12
H'0000 0070
TRAP13
H'0000 0074
TRAP14
H'0000 0078
TRAP15
H'0000 007C
EI
H'0000 0080 (Note 2)
4-10
SM
IE
BPC
0
0
Indeterminate
0
0
PC of the next instruction
Indeterminate
0
PC of the instruction that
generated EIT
Indeterminate
0
PC of the instruction that
generated RIE
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
Indeterminate
0
PC of TRAP instruction + 4
0
0
PC of the next instruction
EIT
4.7 EIT Vector Entry
Ver.0.10

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