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12
Set SIO Receive Control
Register's overrun error bit
and error sum bit to 1
Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing)
The following processing is
automatically executed in hardware
UART receive
operation starts
Transmit
conditions
met?
Y
Start bit
detected
normally?
Y
Set receive status bit to 1
Receive data
Y
Overrun error?
N
Transfer data from SIO Receive Shift
Register to SIO Receive Buffer Register
Parity error or
framing error?
N
Set SIO Receive Control Register's
receive-finished bit to 1
UART reception
completed
12-58
12.7 Receive Operation in UART Mode
N
N
Y
Set SIO Receive Control
Register's corresponding error
bit and receive error sum bit to 1
SERIAL I/O
Ver.0.10
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