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MULTIJUNCTION TIMERS
10
10.3 TOP (Output-related 16-bit Timer)
When after setting the counter and reload register, the timer is enabled (by writing to the enable
bit in software or by external input), it starts counting down from the counter's set value
synchronously with the count clock and when the minimum count is reached, generates an
underflow. This underflow causes the counter to be reloaded with the content of the reload
register and start counting over again. Thereafter, this operation is repeated each time an
underflow occurs. To stop the counter, disable count by writing to the enable bit in software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow,
generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated
each time the counter underflows.
10-66
Ver.0.10
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